EPM5192JC84-1 vs EPM5192GI84 Comparison

Detailed side-by-side comparison of EPM5192JC84-1 by Altera and EPM5192GI84 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192JC84-1 EPM5192GI84
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $15.20 $19.80
Device Type UV-Erasable/OTP Complex Programmable Logic Device (CPLD) UV-Erasable / OTP Complex PLD (CPLD)
Family MAX 5000 MAX 5000
Macrocells 192 192
Propagation Delay (tpd) 40 ns (worst case) β€”
Supply Voltage (Vcc) 4.75 V to 5.25 V (5 V Β±5 %) β€”
Process Technology CMOS EPROM β€”
Operating Temperature Grade Commercial β€”
Package 84-terminal Ceramic Chip Carrier (CQCC84 / J-lead) 84-pin PGA (WPGA, square, through-hole, pin/peg terminals)
JESD-30 Package Code S-CQCC-J84 β€”
Terminal Form J-BEND PIN/PEG
Package Shape SQUARE SQUARE
Mounting Type Surface Mount Through-Hole (PGA socket or PCB pin/peg)
Programmability UV-erasable (window) / OTP in production UV-erasable (windowed) / OTP
Configuration Memory EPROM (non-volatile, instant-on) β€”
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: most legacy PGA parts are non-RoHS]
Logic Array Blocks β€” [DATA_NEEDED: number of LABs]
Package Code β€” WPGA
Operating Voltage (VCC) β€” 5 V (typical)
I/O Logic Compatibility β€” TTL
Temperature Grade β€” Industrial
Programmable Flip-Flop Modes β€” D, T, JK, SR
Programming File Format β€” JEDEC map via MAX+PLUS II / A+PLUS
Propagation Delay β€” [DATA_NEEDED: tPD in ns]
Max User I/O Pins β€” [DATA_NEEDED: usable I/O count for this package]
Operating Temperature Range β€” -40 C to +85 C (industrial)
Lead-Free β€” [DATA_NEEDED: legacy part, likely contains lead]
Number of Terminals β€” 84

Datasheets & Resources

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