EPM5192JC84-1 - 192-Macrocell UV CPLD, 40ns | Altera
MPN: EPM5192JC84-1 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $24.75 | $247.50 |
| 100 | $21 | $2,100.00 |
| 500 | $17.85 | $8,925.00 |
| 1,000 | $15.2 | $15,200.00 |
EPM5192JC84-1 Overview
A CPLD (Complex Programmable Logic Device) is a non-volatile, instant-on programmable logic device built from multiple PAL-like macrocell blocks interconnected by a central programmable switch matrix. CPLDs sit in the broader taxonomy of programmable logic devices alongside SPLDs, FPGAs, and PALs, offering deterministic timing, predictable I/O behavior, and zero-configuration power-up that make them ideal for address decoding, bus interfacing, state-machine control, and peripheral bridging functions.
Key features of the EPM5192JC84-1 include 192 macrocells of logic capacity, 40 ns worst-case pin-to-pin propagation delay, a wide 5 V Β±5 % supply tolerance, and an 84-terminal J-lead ceramic surface-mount package with high-reliability thermal characteristics. CMOS EPROM-based configuration cells provide one-time-programmable (OTP) operation in production, while the UV window variant supports laboratory and prototype erasure. The architecture delivers combinational and registered logic with programmable interconnect, allowing designers to consolidate multiple 74-series MSI/SSI packages into a single device.
Architecturally, the device is built on Altera's CMOS EPROM process with a classic AND-OR array feeding individual product-term allocators per macrocell, a structure that yields deterministic, data-sheet-guaranteed timing independent of routing congestion. Because the configuration is stored in non-volatile EPROM cells, the EPM5192JC84-1 functions as a true instant-on logic device with no boot PROM or in-system programming controller required.
Typical applications include legacy 5 V address decoding, glue logic between microprocessors and peripherals, asynchronous state machines, and bus-interface adapters in industrial and instrumentation equipment. When designing with this part, note that ceramic CQCC84 packages are surface-mountable but require careful thermal profiling and that the UV-erasable variant must be exposed to UV light for ~20 minutes before reprogramming.
Drop-in alternatives for EPM5192JC84-1 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM5192JC84-1 (same form factor and footprint) β differing in Package, Device Type, Mounting Type, Propagation Delay (tPD), Programming Method.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM5192JC84
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM5192JC84-2
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM5192JC-1
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$22.4 / Unit
View Datasheet βEPM5192JC-2
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$22.5 / Unit
View Datasheet βEPM5192JC
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$16.4 / Unit
View Datasheet βEPM5192GC84-1
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$14.2 / Unit
View Datasheet βEPM5192GI84
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$19.8 / Unit
View Datasheet βEPM5192JC84-1 Maximum Ratings & Electrical Characteristics
| Device Type | UV-Erasable/OTP Complex Programmable Logic Device (CPLD) |
| Family | MAX 5000 |
| Macrocells | 192 |
| Propagation Delay (tpd) | 40 ns (worst case) |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V (5 V Β±5 %) |
| Process Technology | CMOS EPROM |
| Operating Temperature Grade | Commercial |
| Package | 84-terminal Ceramic Chip Carrier (CQCC84 / J-lead) |
| JESD-30 Package Code | S-CQCC-J84 |
| Terminal Form | J-BEND |
| Package Shape | SQUARE |
| Mounting Type | Surface Mount |
| Programmability | UV-erasable (window) / OTP in production |
| Configuration Memory | EPROM (non-volatile, instant-on) |
EPM5192JC84-1 Pin Configuration
| Pin 1 | GND β Ground reference |
| Pin 2 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 3 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 4 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 5 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 6 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 7 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 8 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 9 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 10 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 11 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 12 | GND β Ground reference |
| Pin 13 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 14 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 15 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 16 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 17 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 18 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 19 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 20 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 21 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 22 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 23 | GND β Ground reference |
| Pin 24 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 25 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 26 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 27 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 28 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 29 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 30 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 31 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 32 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 33 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 34 | GND β Ground reference |
| Pin 35 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 36 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 37 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 38 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 39 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 40 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 41 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 42 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 43 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 44 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 45 | GND β Ground reference |
| Pin 46 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 47 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 48 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 49 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 50 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 51 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 52 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 53 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 54 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 55 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 56 | GND β Ground reference |
| Pin 57 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 58 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 59 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 60 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 61 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 62 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 63 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 64 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 65 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 66 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 67 | GND β Ground reference |
| Pin 68 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 69 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 70 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 71 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 72 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 73 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 74 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 75 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 76 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 77 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 78 | GND β Ground reference |
| Pin 79 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 80 | VCC β +5 V supply (4.75 V to 5.25 V) |
| Pin 81 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 82 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 83 | I/O β General-purpose I/O pin (macrocell I/O) |
| Pin 84 | I/O β General-purpose I/O pin (macrocell I/O) |
Typical Applications
EPM5192JC84-1 is suitable for 6 applications: 5 V Address Decoding Glue Logic, Legacy Microprocessor Bus Interfacing, Asynchronous State Machine Controllers, Peripheral Bridging and Protocol Conversion, Test and Measurement Instrumentation Logic, Legacy Industrial Control I/O Expansion.
5 V Address Decoding Glue Logic
The EPM5192JC84-1 fits 5 V address-decoding applications because of its 192-macrocell density, 40 ns worst-case propagation delay, and 5 V Β±5 % supply tolerance. With 192 macrocells it can decode large peripheral or memory address maps and generate chip-select strobes for multiple devices in a single package. Placed between a microprocessor bus and memory/peripheral devices, it replaces several 74LS138/74LS139 decoder trees; unlike an FPGA it provides instant-on non-volatile configuration, so the system boots into a known decoder state without bootloader delay. Designers should budget for the 40 ns tpd when computing the address-to-CSK skew and place the CPLD close to the devices it decodes to minimize board-level propagation.
Recommended
Legacy Microprocessor Bus Interfacing
The EPM5192JC84-1 is well suited to legacy 8-bit and 16-bit microprocessor bus-interface tasks thanks to its 5 V-tolerant CMOS EPROM I/O and deterministic 40 ns propagation delay. With 192 macrocells the part can implement wait-state generators, bus-watchdog timers, byte-swapping muxes, and read/write strobe combiners in a single device, replacing 4 to 6 MSI packages. Because the configuration is non-volatile, the interface logic is active immediately at power-on, which is critical for cold-boot systems that cannot tolerate FPGA configuration latency. The CQCC84 ceramic package also tolerates the wider industrial temperature range typical of legacy industrial controllers.
Recommended
Asynchronous State Machine Controllers
The EPM5192JC84-1 is a strong fit for asynchronous and synchronous state-machine controllers in industrial equipment because of its EPROM-based configuration and guaranteed 40 ns worst-case timing. Each macrocell contains a flip-flop with configurable clock, reset, and preset, so 192 flip-flops can implement complex FSMs for protocol handling, sequencing, or machine control in a single package. The ceramic CQCC84 package withstands harsh industrial environments, while the non-volatile instant-on configuration eliminates the boot-up delays and configuration-bitstream risks of SRAM-based FPGAs. Designers should use the Quartus or MAX+PLUS II fitter to balance macrocell utilization and verify that worst-case tpd plus I/O delay still meets the FSM cycle time.
Recommended
Peripheral Bridging and Protocol Conversion
The EPM5192JC84-1 fits peripheral-bridging and protocol-conversion duties because 192 macrocells are sufficient to bridge legacy 8-bit parallel buses to serial peripherals or to convert between asynchronous and synchronous protocols. The 40 ns tpd gives the device enough timing margin to act as a transparent bus bridge without stalling the master, while the 5 V I/O is directly compatible with TTL/CMOS peripherals of the 1990s. The non-volatile EPROM configuration means the bridge is functional the instant VCC crosses 4.75 V, eliminating FPGA configuration overhead. Suggested adjacent parts: 8255 PPI, 16550 UART, or an 8-bit microcontroller as the peripheral endpoint.
Recommended
Test and Measurement Instrumentation Logic
The EPM5192JC84-1 is a good match for test-and-measurement front-panel and backplane glue logic because its 192 macrocells can implement counter/divider chains, pulse generators, scan-multiplexer control, and trigger-conditioning logic in a single device. The 40 ns propagation delay supports timing generators up to ~10 MHz, while the 5 V Β±5 % supply tolerance is robust against the noisy rails typical of bench instruments. The ceramic CQCC84 package also provides the long-term reliability expected in laboratory-grade equipment. Use the JTAG-style programming pins to update the configuration during calibration, and pair with a precision ADC such as the AD574A for a complete instrument front end.
Recommended
Legacy Industrial Control I/O Expansion
The EPM5192JC84-1 fits legacy industrial control I/O-expansion applications because its 192 macrocells can implement latched 24 V-compatible input scanners, output mux/demux logic, and isolated-control interfaces. The ceramic CQCC84 package operates reliably across industrial temperature ranges and the EPROM-based configuration retains logic state through power cycles without battery backup - a major reliability advantage over SRAM FPGAs. With 40 ns worst-case tpd the device can scan and refresh dozens of I/O points within a single PLC scan cycle. Designers should place optocoupler isolation upstream of the EPM5192 and follow the Altera MAX 5000 decoupling guidelines (one 0.1 Β΅F per VCC pin) for noise immunity.
Recommended
Recommended Products Summary
Engineering reference data for EPM5192JC84-1 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5192JC84 | EPM5192JC84-2 | EPM5192JC-1 | EPM5192JC-2 | EPM5192GI84 |
|---|---|---|---|---|---|---|
| Package | CQCC84 (J-lead) ceramic | CQCC84 (J-lead) ceramic - same | CQCC84 (J-lead) ceramic - same | CQCC84 (J-lead) ceramic - same | CQCC84 (J-lead) ceramic - same | CQCC84 (J-lead) ceramic - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 192 | 192 | 192 | 192 | 192 | 192 |
| Propagation Delay (tpd) | 40 ns | 55 ns | 25 ns | 40 ns | 25 ns | 40 ns |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Temperature Grade | Commercial | Commercial | Commercial | Commercial | Commercial | Industrial |
| Process / Memory | CMOS EPROM | CMOS EPROM | CMOS EPROM | CMOS EPROM | CMOS EPROM | CMOS EPROM |
| Pin Compatibility | 84-pin CQCC84 (J-lead) | 100% pin-compatible | 100% pin-compatible | 100% pin-compatible | 100% pin-compatible | 100% pin-compatible |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- 40 ns speed grade in CQCC84 ceramic package (vs EPM5192JC84)
- Faster alternative in the same package (vs EPM5192JC84-2)
- Industrial-temp upgrade path in the same footprint (vs EPM5192GI84)
Design Notes
Place one 0.1 Β΅F decoupling capacitor as close as possible to every VCC pin of the EPM5192JC84-1 and a single 1 Β΅F to 10 Β΅F bulk capacitor near the package power-entry point. The MAX 5000 family datasheet recommends a maximum of 1 to 2 inches of trace between each VCC pin and its decoupling cap. Ground returns should be low-impedance: use a ground plane under the CQCC84 footprint and stitch multiple vias around the package perimeter to reduce ground bounce on high-fanout outputs.
Do not exceed the 5 V Β±5 % supply tolerance - operation above 5.25 V may corrupt the EPROM configuration cells over time, while operation below 4.75 V can cause timing violations or loss of macrocell state. Programming the part requires a 12.5 V VPP pulse on the appropriate JTAG pin and a fully MAX+PLUS II-generated JEDEC file; using a Quartus-generated JEDEC for a MAX 5000 design without the legacy device support installed is a common failure mode. UV erasure of windowed variants requires ~20 minutes of exposure to a calibrated UV lamp (12 mW/cmΒ² @ 253.7 nm).
Estimated: the ceramic CQCC84 package has a typical ΞΈJA of approximately 35 to 45 C/W in still air. With VCC = 5.0 V and the device fully utilized at 192 macrocells switching at 5 MHz, the CMOS EPROM core dissipates an estimated 200 to 400 mW; junction rise above ambient is therefore ~7 to 18 C, well within the commercial operating range. Designers should still avoid placing heat-generating components adjacent to the CQCC84 footprint and should provide copper pours tied to GND on inner PCB layers to spread any localized self-heating.
Compliance Information
RoHS/REACH compliance data not provided in the verified web data; mark as unknown. AEC-Q100 is not applicable to a logic CPLD without automotive qualification. Ceramic CQCC84 packages historically contain lead-bearing terminations; verify RoHS status with the distributor before placing compliant orders.
