EPM7128ELC84-20 vs EPM7160ELC84-20 Comparison
Detailed side-by-side comparison of EPM7128ELC84-20 by Altera and EPM7160ELC84-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128ELC84-20
EPM7128ELC84-20 - MAX 7000 CPLD, 128MC, 20ns, 5V, PLCC-84 | Altera
EPM7128ELC84-20 ObsoleteIntel
EPM7160ELC84-20
EPM7160ELC84-20 - MAX 7000 CPLD, 160 Macrocells, 20ns | Intel
EPM7160ELC84-20 ObsoleteSpecification Comparison
| Parameter | EPM7128ELC84-20 | EPM7160ELC84-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $24.20 | $16.95 |
| Series | MAX 7000 | β |
| Device Family | EPM7128 (CPLD) | β |
| Number of Macrocells | 128 | β |
| Number of Usable Gates | 2500 | β |
| Number of User I/Os | 68 | β |
| Number of Logic Array Blocks (LABs) | 8 | β |
| Propagation Delay (tPD) | 20 ns | β |
| Maximum Frequency (fCNT) | 62.5 MHz | β |
| Supply Voltage (VCC) | 5 V | 5.0 V |
| Supply Voltage Tolerance | 4.75 V to 5.25 V | β |
| Technology | CMOS, EEPROM-based (non-volatile) | CMOS EEPROM |
| Programmable Interface | IEEE Std. 1149.1 (JTAG) | β |
| Package Type | PLCC-84 (J-Lead, J-bend) | β |
| Mounting Type | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| Operating Temperature | 0C to +70C (commercial) | β |
| RoHS Status | Contains lead (pre-RoHS, SnPb finish) | [DATA_NEEDED: RoHS compliance per specific part marking] |
| Family | β | MAX 7000 |
| Macrocells | β | 160 |
| Logic Array Blocks | β | 4 |
| Usable Gates | β | 3,200 |
| User I/O Pins | β | 64 |
| Pin-to-Pin Delay (tPD) | β | 20 ns |
| Operating Temperature (Commercial) | β | 0C to +70C |
| Programming Interface | β | IEEE 1149.1 JTAG (ISP) |
| In-System Programmable | β | Yes (5.0-V ISP) |
| Package | β | PLCC-84 (windowed ceramic carrier not applicable - plastic) |
| Architecture | β | Second-generation MAX |
| Global Clock Inputs | β | 4 |
| Logic Element Type | β | EEPROM-based macrocell |