EPM7160ELC84-20 - MAX 7000 CPLD, 160 Macrocells, 20ns | Intel
MPN: EPM7160ELC84-20 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.2 | $252.00 |
| 100 | $21.75 | $2,175.00 |
| 500 | $18.4 | $9,200.00 |
| 1,000 | $16.95 | $16,950.00 |
EPM7160ELC84-20 Overview
A CPLD (Complex Programmable Logic Device) is a non-volatile, instant-on programmable logic device that combines the architecture of multiple PAL/GAL-like PLDs on a single chip with a programmable interconnect matrix. CPLDs occupy the middle ground between small discrete logic ICs (gates, muxes, flip-flops) and larger FPGAs: they offer deterministic timing, sub-100 ns propagation delays, and zero configuration time at power-up. In the broader system hierarchy, the MAX 7000 CPLD sits between 74-series discrete logic and SRAM-based FPGAs, serving as the ideal integration point for board-level glue logic, address decoding, interrupt steering, and I/O expansion. The MAX 7000 series is a foundational product line that helped popularize ISP and JTAG-based programming in mainstream digital design.
Key features include 3,200 usable gates, 64 I/O pins with 5-V tolerant I/O on most variants, four global clock inputs, and a JTAG-compliant boundary-scan test interface. The device operates from a single 5.0 V supply (VCCINT and VCCIO combined) with low standby current, and supports commercial (0C to +70C) operating temperature ranges. Programming is performed via the JTAG port using the ByteBlaster or BitBlaster download cable, or in-system from a microcontroller-driven JTAG master, eliminating the need for a dedicated programmer.
Typical applications include peripheral glue logic in microprocessor and DSP systems, address decoding and chip-select generation, bus arbitration and interrupt prioritization, register-based I/O expansion, and JTAG-driven board-level test infrastructure. The 84-pin PLCC package is socket-friendly, supporting both production assembly and easy breadboard prototyping for engineering development.
When designing with this device, designers should provide adequate decoupling (typically 0.1 uF per VCC pin plus a 10 uF bulk capacitor) and follow Altera's JTAG chain recommendations when multiple devices share the same programming port. The PLCC-84 footprint is a JEDEC-standard land pattern, but designers migrating to lead-free assemblies should verify the soldering profile against the JEDEC J-STD-020 moisture sensitivity level (MSL) rating.
This page synthesizes distributor pricing, drop-in alternatives within the same PLCC-84 footprint, and practical design notes not found on a single manufacturer page.
Drop-in alternatives for EPM7160ELC84-20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM7160ELC84-20 (same form factor and footprint) — differing in Package, RoHS Status, Operating Temperature, Mounting Type, Usable Gates.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM7160ELC84-15
✅ Drop-In✓ In Stock
$5.95 / Unit
View Datasheet →EPM7160ELI84-20
✅ Drop-In✓ In Stock
$11.1 / Unit
View Datasheet →EPM7160SLC84-6
✅ Drop-In✓ In Stock
$15.86 / Unit
View Datasheet →EPM7128ELC84-20
✅ Drop-In✓ In Stock
$24.2 / Unit
View Datasheet →EPM7160ELC84-20 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000 |
| Macrocells | 160 |
| Logic Array Blocks | 4 |
| Usable Gates | 3,200 |
| User I/O Pins | 64 |
| Pin-to-Pin Delay (tPD) | 20 ns |
| Supply Voltage (VCC) | 5.0 V |
| Operating Temperature (Commercial) | 0C to +70C |
| Programming Interface | IEEE 1149.1 JTAG (ISP) |
| In-System Programmable | Yes (5.0-V ISP) |
| Package | PLCC-84 (windowed ceramic carrier not applicable - plastic) |
| Technology | CMOS EEPROM |
| Architecture | Second-generation MAX |
| Mounting Type | Surface Mount (PLCC socket compatible) |
| Global Clock Inputs | 4 |
| Logic Element Type | EEPROM-based macrocell |
EPM7160ELC84-20 Pin Configuration
| Pin 1 | I/O — User I/O pin (macrocell) |
| Pin 2 | I/O — User I/O pin (macrocell) |
| Pin 3 | I/O — User I/O pin (macrocell) |
| Pin 4 | I/O — User I/O pin (macrocell) |
| Pin 5 | I/O — User I/O pin (macrocell) |
| Pin 6 | I/O — User I/O pin (macrocell) |
| Pin 7 | I/O — User I/O pin (macrocell) |
| Pin 8 | I/O — User I/O pin (macrocell) |
| Pin 9 | I/O — User I/O pin (macrocell) |
| Pin 10 | I/O — User I/O pin (macrocell) |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O pin (macrocell) |
| Pin 13 | I/O — User I/O pin (macrocell) |
| Pin 14 | I/O — User I/O pin (macrocell) |
| Pin 15 | I/O — User I/O pin (macrocell) |
| Pin 16 | I/O — User I/O pin (macrocell) |
| Pin 17 | I/O — User I/O pin (macrocell) |
| Pin 18 | I/O — User I/O pin (macrocell) |
| Pin 19 | I/O — User I/O pin (macrocell) |
| Pin 20 | I/O — User I/O pin (macrocell) |
| Pin 21 | VCC — 5.0 V supply |
| Pin 22 | I/O — User I/O pin (macrocell) |
| Pin 23 | I/O — User I/O pin (macrocell) |
| Pin 24 | I/O — User I/O pin (macrocell) |
| Pin 25 | I/O — User I/O pin (macrocell) |
| Pin 26 | I/O — User I/O pin (macrocell) |
| Pin 27 | I/O — User I/O pin (macrocell) |
| Pin 28 | I/O — User I/O pin (macrocell) |
| Pin 29 | I/O — User I/O pin (macrocell) |
| Pin 30 | I/O — User I/O pin (macrocell) |
| Pin 31 | GND — Ground |
| Pin 32 | I/O — User I/O pin (macrocell) |
| Pin 33 | I/O — User I/O pin (macrocell) |
| Pin 34 | I/O — User I/O pin (macrocell) |
| Pin 35 | I/O — User I/O pin (macrocell) |
| Pin 36 | I/O — User I/O pin (macrocell) |
| Pin 37 | I/O — User I/O pin (macrocell) |
| Pin 38 | I/O — User I/O pin (macrocell) |
| Pin 39 | I/O — User I/O pin (macrocell) |
| Pin 40 | I/O — User I/O pin (macrocell) |
| Pin 41 | VCC — 5.0 V supply |
| Pin 42 | I/O — User I/O pin (macrocell) |
| Pin 43 | I/O — User I/O pin (macrocell) |
| Pin 44 | I/O — User I/O pin (macrocell) |
| Pin 45 | I/O — User I/O pin (macrocell) |
| Pin 46 | I/O — User I/O pin (macrocell) |
| Pin 47 | I/O — User I/O pin (macrocell) |
| Pin 48 | I/O — User I/O pin (macrocell) |
| Pin 49 | I/O — User I/O pin (macrocell) |
| Pin 50 | I/O — User I/O pin (macrocell) |
| Pin 51 | GND — Ground |
| Pin 52 | I/O — User I/O pin (macrocell) |
| Pin 53 | I/O — User I/O pin (macrocell) |
| Pin 54 | I/O — User I/O pin (macrocell) |
| Pin 55 | I/O — User I/O pin (macrocell) |
| Pin 56 | I/O — User I/O pin (macrocell) |
| Pin 57 | I/O — User I/O pin (macrocell) |
| Pin 58 | I/O — User I/O pin (macrocell) |
| Pin 59 | I/O — User I/O pin (macrocell) |
| Pin 60 | I/O — User I/O pin (macrocell) |
| Pin 61 | VCC — 5.0 V supply |
| Pin 62 | I/O — User I/O pin (macrocell) |
| Pin 63 | I/O — User I/O pin (macrocell) |
| Pin 64 | I/O — User I/O pin (macrocell) |
| Pin 65 | I/O — User I/O pin (macrocell) |
| Pin 66 | I/O — User I/O pin (macrocell) |
| Pin 67 | I/O — User I/O pin (macrocell) |
| Pin 68 | I/O — User I/O pin (macrocell) |
| Pin 69 | I/O — User I/O pin (macrocell) |
| Pin 70 | I/O — User I/O pin (macrocell) |
| Pin 71 | GND — Ground |
| Pin 72 | I/O — User I/O pin (macrocell) |
| Pin 73 | I/O — User I/O pin (macrocell) |
| Pin 74 | I/O — User I/O pin (macrocell) |
| Pin 75 | I/O — User I/O pin (macrocell) |
| Pin 76 | I/O — User I/O pin (macrocell) |
| Pin 77 | TDI — JTAG Test Data In |
| Pin 78 | TMS — JTAG Test Mode Select |
| Pin 79 | TCK — JTAG Test Clock |
| Pin 80 | TDO — JTAG Test Data Out |
| Pin 81 | I/O — User I/O pin (macrocell) |
| Pin 82 | I/O — User I/O pin (macrocell) |
| Pin 83 | I/O — User I/O pin (macrocell) |
| Pin 84 | GND — Ground |
Typical Applications
EPM7160ELC84-20 is suitable for 7 applications: Microprocessor Gl ue Logic and Chip-Select Decoding, Address Decoding and Memory Bank Selection, Bus Arbitration and Interrupt Steering, Register-Based I/O Expansion, JTAG-Driven Board-Level Test Infrastructure, State Machine and Protocol Conversion, Legacy Industrial Control Replacement.
Microprocessor Gl ue Logic and Chip-Select Decoding
The EPM7160ELC84-20 fits this application because its 160 macrocells and 64 user I/O pins provide ample capacity to integrate scattered 74-series glue logic into a single programmable device. With 20 ns pin-to-pin delay and 5.0-V tolerant I/O, the CPLD directly interfaces with 5-V microprocessors and peripherals without level shifters, while deterministic timing ensures chip-select signals are generated with predictable setup/hold margins. Compared to discrete logic ICs, the EPM7160ELC84-20 reduces board area, simplifies BOM, and allows late-stage design changes via JTAG re-programming. In a typical design it replaces dozens of AND/OR gates, latches, and decoders with one device, while retaining the JTAG-driven ISP that enables field firmware updates.
Recommended
Address Decoding and Memory Bank Selection
The EPM7160ELC84-20 is well suited for address decoding in microprocessor and DSP systems where multiple memory banks, peripherals, or I/O devices must be selected via individual chip-enable lines. Its 64 user I/O pins and 160 macrocells can decode wide address buses (24+ address lines) and generate dozens of unique chip-select outputs, replacing entire decoder ICs. The 20 ns propagation delay is fast enough to keep memory-access wait states at zero for microprocessors running up to approximately 25 MHz. Compared to discrete 74LS138/139 decoders, the CPLD consolidates multiple decode functions into one device and lets designers re-map the memory map via JTAG without board rework.
Recommended
Bus Arbitration and Interrupt Steering
The EPM7160ELC84-20 fits bus arbitration and interrupt-priority encoding in multi-master systems because its macrocell-based architecture provides deterministic, fixed-latency logic with no race conditions. With 64 I/O pins and four global clock inputs, it can monitor multiple bus-request and grant signals simultaneously while steering prioritized interrupts to a host CPU. The MAX 7000 architecture's predictable timing simplifies worst-case latency analysis required for arbitration protocols. Compared to discrete priority encoders and latches, the CPLD adds JTAG visibility into internal states for debug and supports in-system re-tuning of arbitration policies.
Recommended
Register-Based I/O Expansion
The EPM7160ELC84-20 enables register-based I/O expansion for microcontrollers and microprocessors with insufficient native GPIO pins by emulating parallel-port expanders, shift-register chains, or addressable I/O blocks. Each of its 64 user I/O pins can be configured as input, output, or bidirectional, with optional weak pull-ups, supporting direct LED driving, relay control, or button-matrix scanning. With 5.0-V tolerant I/O, the CPLD interfaces directly with 5-V peripherals without external buffers. Compared to dedicated I/O expander ICs, the EPM7160ELC84-20 offers more flexibility in pin assignment and timing behavior via JTAG reconfiguration.
Recommended
JTAG-Driven Board-Level Test Infrastructure
The EPM7160ELC84-20's built-in IEEE 1149.1 JTAG interface makes it a natural boundary-scan controller and test-access port for board-level manufacturing test. By configuring its I/O pins in boundary-scan mode, the CPLD can interconnect nets between JTAG-controlled devices, isolating faults and exercising signals without physical probe access. The 5.0-V ISP capability also lets manufacturers program the device on-board during the assembly flow, eliminating pre-programming steps. Compared to dedicated boundary-scan controllers, the EPM7160ELC84-20 doubles as functional logic plus JTAG infrastructure in one device.
Recommended
State Machine and Protocol Conversion
The EPM7160ELC84-20 fits finite state machine and protocol-bridge applications such as UART-to-parallel, SPI-to-I2C, or parallel-to-PCM conversion because its macrocells are optimized for registered logic with clock-enable and reset control. The 4 Logic Array Blocks partition complex state machines into manageable sections, while 20 ns delay supports protocols up to about 25 MHz. Compared to microcontrollers running state-machine firmware, the CPLD offers deterministic timing unaffected by interrupt latency, and starts executing at power-on without code-boot delays. JTAG ISP allows protocol upgrades in the field.
Recommended
Legacy Industrial Control Replacement
The EPM7160ELC84-20 is commonly used as a form-fit-function replacement for obsolete discrete logic boards in legacy industrial control systems because its PLCC-84 package fits existing sockets and footprints. With 160 macrocells and 64 I/O pins, it can replicate dozens of legacy 74LS/74HC ICs in a single device, simplifying maintenance and reducing downtime. Its commercial temperature grade suits factory-floor environments. Compared to redesigning around modern FPGAs, the EPM7160ELC84-20 enables drop-in retrofits that preserve wiring, connectors, and system behavior while modernizing internal logic.
Recommended
Recommended Products Summary
Engineering reference data for EPM7160ELC84-20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7160ELC84-15 | EPM7160ELI84-20 | EPM7160SLC84-6 | EPM7128ELC84-20 |
|---|---|---|---|---|---|
| Package | PLCC-84 | PLCC-84 - same | PLCC-84 - same | PLCC-84 - same footprint | PLCC-84 - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Macrocells | 160 | 160 | 160 | 160 | 128 (-20%) |
| Pin-to-Pin Delay (tPD) | 20 ns | 15 ns (faster) | 20 ns (same) | 6 ns (faster) | 20 ns (same) |
| Supply Voltage (VCC) | 5.0 V | 5.0 V (compatible) | 5.0 V (compatible) | 3.3 V (NOT compatible) | 5.0 V (compatible) |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C | -40C to +85C (Industrial) | 0C to +70C | 0C to +70C |
| User I/O Pins | 64 | 64 | 64 | 64 | 64 |
| JTAG / ISP | Yes (IEEE 1149.1) | Yes | Yes | Yes | Yes |
Key Differentiators
- Drop-in compatibility on PLCC-84 footprint across the MAX 7000 family (vs EPM7128ELC84-20)
- Industrial-temperature variant available on the same PLCC-84 pinout (vs EPM7160ELI84-20)
- 5.0-V tolerant I/O directly interfaces with 5-V microprocessors (vs EPM7160SLC84-6)
- Faster speed grade available on same PLCC-84 footprint (vs EPM7160ELC84-15)
Design Notes
The EPM7160ELC84-20 requires a stable 5.0 V ±5% supply at VCC pins 21, 41, 61, and 84. Place one 0.1 uF ceramic decoupling capacitor adjacent to each VCC pin and a single 10 uF bulk tantalum or low-ESR ceramic capacitor near the device. Insufficient decoupling can cause ISP programming failures and intermittent logic errors during high-frequency I/O switching. VCC must rise monotonically on power-up for reliable initialization - add a reset supervisor if the upstream regulator has slow or non-monotonic startup.
For PLCC-84 layout, follow the JEDEC standard land pattern with 1.27 mm pitch and exposed pad geometry compatible with both socketed and direct-solder assembly. When using a PLCC socket, retain the socket's recommended PCB pad pattern and ensure mechanical retention clips are present to prevent vibration-induced contact failures. Keep JTAG traces (TDI, TDO, TMS, TCK) short and route them on an inner or outer layer with no stubs; add 10 kohm pull-ups on TMS and TDI per JTAG convention to keep the TAP controller in a known state at power-up.
Do not substitute the EPM7160ELC84-20 with the EPM7160SLC84-6 directly - despite sharing the PLCC-84 footprint, the SL variant operates at 3.3 V and will be damaged by a 5.0 V supply. When migrating to industrial temperature, the EPM7160ELI84-20 is drop-in compatible but has slightly different DC characteristics; verify timing margins across the full -40C to +85C range. For unused I/O pins, configure them as outputs driving low or as inputs with weak pull-ups enabled - never leave them floating to avoid quiescent-current spikes.
The MAX 7000 macrocell output slew rate is approximately 1-2 ns; output pins can generate fast edges that couple into adjacent traces. Maintain at least 3W (where W = trace width to substrate) spacing between high-speed outputs and sensitive analog signals, and use a ground plane on an adjacent layer to provide return-current paths. For clock outputs above 33 MHz, consider adding 22-33 ohm series damping resistors to reduce reflections on longer traces.
Compliance Information
EPM7160ELC84-20 is a legacy EOL product from the MAX 7000 family (introduced mid-1990s); original launch predates many modern compliance reporting frameworks. RoHS/REACH status depends on the specific date code and lot origin - consult the manufacturer certificate of conformance for the exact shipment. Not AEC-Q100 qualified (commercial/industrial grade only).
