EPM7128SQC100-7 vs EPM7128SQC100-15 Comparison
Detailed side-by-side comparison of EPM7128SQC100-7 by Intel and EPM7128SQC100-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128SQC100-7
EPM7128SQC100-7 - 128-Macro 5V CPLD, 7.5ns, 100-Pin PQFP | Altera (Intel)
EPM7128SQC100-7 ObsoleteAltera
EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel
EPM7128SQC100-15 β Last Time BuySpecification Comparison
| Parameter | EPM7128SQC100-7 | EPM7128SQC100-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.85 | $8.20 |
| Product Type | CPLD - Complex Programmable Logic Device | β |
| Family | MAX 7000S | MAX 7000 |
| Macro Cells | 128 | β |
| Usable Gates | 2,500 | β |
| User I/Os | 84 | 84 |
| Logic Elements / LABs | 4 Logic Array Blocks (LABs) | β |
| Propagation Delay (tPD) | 7.5 ns | β |
| Maximum Internal Frequency | 125 MHz | β |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | β |
| Technology | CMOS, EEPROM-based, non-volatile | β |
| Package | 100-pin PQFP (Plastic Quad Flat Pack) | 100-pin PQFP (Plastic Quad Flat Pack) |
| Programming Interface | JTAG (IEEE Std 1149.1), in-system programmable | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (Commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Non-RoHS (legacy SnPb package) | Non-compliant (SnPb lead finish - legacy PQFP) |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macrocells | β | 128 |
| Logic Array Blocks (LABs) | β | 4 (16 macrocells each) |
| Pin-to-Pin Delay (tPD) | β | 15 ns |
| Maximum Frequency (fMAX) | β | [DATA_NEEDED: fMAX value] |
| Typical Gate Count | β | 2,500 gates |
| Supply Voltage (VCCINT) | β | 5 V (5% tolerance) |
| Programming Technology | β | EEPROM (in-system programmable via JTAG) |
| JTAG Interface | β | IEEE Std. 1149.1 compliant |
| MSL Level | β | 3 (168 hours) |