EPM7128SQC100-7N vs EPM7128SQC100-10 Comparison

Detailed side-by-side comparison of EPM7128SQC100-7N by Intel and EPM7128SQC100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7128SQC100-7N EPM7128SQC100-10
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $7.10 $9.85
Family MAX 7000S MAX 7000S
Device Type CPLD - Complex Programmable Logic Device CPLD (Complex Programmable Logic Device)
Program Memory Type EEPROM β€”
Number of Macrocells 128 β€”
Number of Logic Array Blocks 8 β€”
Number of Global Clocks 2 β€”
Product Terms per Macrocell 32 β€”
Usable Gates 2,500 β€”
System Gates 5,000 (max) β€”
Maximum User I/Os 84 β€”
Pin-to-Pin Delay (tPD) 7.5 ns β€”
Counter Speed 175.4 MHz β€”
In-System Programmability Yes (IEEE 1149.1 JTAG) β€”
Operating Voltage (Core) 5.0 V β€”
I/O Standard Support multiVolt (2.5V, 3.3V, 5.0V) β€”
Package 100-pin PQFP (QFP-100) 100-pin PQFP (Plastic Quad Flat Pack)
Operating Temperature 0C to +70C (commercial) 0C to +70C (commercial)
RoHS Status Compliant (lead-free 'N' suffix) [DATA_NEEDED: rohs_status]
Process Technology 0.30 Β΅m CMOS EEPROM 5V CMOS, EEPROM-based
Security Bit Programmable (one per device) β€”
Macro Cells β€” 128
Logic Elements / Gates β€” 2,500 usable gates
Maximum User I/O β€” 84
Logic Array Blocks (LABs) β€” 16
Maximum Operating Frequency β€” 100 MHz
Pin-to-Pin Logic Delay (tPD) β€” 10 ns
Supply Voltage β€” 5 V
Programmability β€” In-System Programmable (ISP) via JTAG
Mounting Type β€” Surface Mount

Datasheets & Resources

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