EPM7128SQC100-7N vs EPM7128SQC100-7 Comparison

Detailed side-by-side comparison of EPM7128SQC100-7N by Intel and EPM7128SQC100-7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EPM7128SQC100-7

EPM7128SQC100-7 - 128-Macro 5V CPLD, 7.5ns, 100-Pin PQFP | Altera (Intel)

EPM7128SQC100-7 Obsolete

Specification Comparison

Parameter EPM7128SQC100-7N EPM7128SQC100-7
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $7.10 $10.85
Family MAX 7000S MAX 7000S
Device Type CPLD - Complex Programmable Logic Device β€”
Program Memory Type EEPROM β€”
Number of Macrocells 128 β€”
Number of Logic Array Blocks 8 β€”
Number of Global Clocks 2 β€”
Product Terms per Macrocell 32 β€”
Usable Gates 2,500 2,500
System Gates 5,000 (max) β€”
Maximum User I/Os 84 β€”
Pin-to-Pin Delay (tPD) 7.5 ns β€”
Counter Speed 175.4 MHz β€”
In-System Programmability Yes (IEEE 1149.1 JTAG) β€”
Operating Voltage (Core) 5.0 V β€”
I/O Standard Support multiVolt (2.5V, 3.3V, 5.0V) β€”
Package 100-pin PQFP (QFP-100) 100-pin PQFP (Plastic Quad Flat Pack)
Operating Temperature 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
RoHS Status Compliant (lead-free 'N' suffix) Non-RoHS (legacy SnPb package)
Process Technology 0.30 Β΅m CMOS EEPROM β€”
Security Bit Programmable (one per device) β€”
Product Type β€” CPLD - Complex Programmable Logic Device
Macro Cells β€” 128
User I/Os β€” 84
Logic Elements / LABs β€” 4 Logic Array Blocks (LABs)
Propagation Delay (tPD) β€” 7.5 ns
Maximum Internal Frequency β€” 125 MHz
Supply Voltage (VCCINT/VCCIO) β€” 5.0 V
Technology β€” CMOS, EEPROM-based, non-volatile
Programming Interface β€” JTAG (IEEE Std 1149.1), in-system programmable
Mounting Type β€” Surface Mount

Datasheets & Resources

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