EPM7128SQI100-10N vs EPM7128STI100-10N Comparison

Detailed side-by-side comparison of EPM7128SQI100-10N by Intel and EPM7128STI100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM7128STI100-10N

EPM7128STI100-10N - 128-Macrocell CPLD, 10ns, 100-pin TQFP | Altera

EPM7128STI100-10N Obsolete

Specification Comparison

Parameter EPM7128SQI100-10N EPM7128STI100-10N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $15.90 $9.85
Family MAX 7000S MAX 7000S
Device Type CPLD - Complex Programmable Logic Device β€”
Macrocells 128 128
Usable Gates 2,500 (up to 5,000 usable in family) 2,500 (up to 5,000 family max)
Logic Array Blocks (LABs) 4 8
Maximum User I/Os 84 β€”
Pin-to-Pin Logic Delay (tPD) 10 ns 10 ns
Maximum Operating Frequency 100 MHz β€”
Counter Frequency (family max) 175.4 MHz β€”
Supply Voltage - Core (VCCINT) 5.0 V β€”
Supply Voltage - I/O (VCCIO) 2.5 V / 3.3 V / 5.0 V (multiVolt) β€”
Technology CMOS, EEPROM-based configuration β€”
Package 100-pin PQFP (Plastic Quad Flat Pack) 100-pin TQFP
Mounting Type Surface Mount Surface Mount
Operating Temperature -40C to +85C (Industrial grade, 'I' suffix) -40C to +85C (Industrial)
Programming Interface JTAG (IEEE Std. 1149.1) / ByteBlaster β€”
RoHS Compliance Compliant (lead-free, 'N' suffix) β€”
Architecture β€” CMOS EEPROM-based CPLD
Maximum User I/O β€” 84
Maximum Counter Frequency β€” 175.4 MHz
Supply Voltage (VCC) β€” 5 V
In-System Programmability β€” Yes (JTAG IEEE 1149.1)
JTAG Boundary-Scan β€” Yes (BST)
MSL Level β€” [DATA_NEEDED: MSL level]
RoHS Status β€” [DATA_NEEDED: RoHS status]
Open-Drain I/O Option β€” Available (per MAX 7000A feature set)

Datasheets & Resources

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