EPM7160ELC84-15 vs EPM7160ELC84-20 Comparison
Detailed side-by-side comparison of EPM7160ELC84-15 by Intel and EPM7160ELC84-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7160ELC84-15 | EPM7160ELC84-20 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5.95 | $16.95 |
| Family | MAX 7000 | MAX 7000 |
| Product Type | CPLD - Complex Programmable Logic Device | β |
| Architecture | EEPROM-based, second-generation MAX | Second-generation MAX |
| Usable Gates | 3,200 | 3,200 |
| Macrocells | 160 | 160 |
| Logic Array Blocks | 4 | 4 |
| Maximum I/O Pins | 36 | β |
| Pin-to-Pin Delay | 15 ns | β |
| Counter Frequency | 76.9 MHz | β |
| Supply Voltage (Vcc) | 5 V | β |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | β |
| Package Type | 84-pin PLCC (J-Lead) | β |
| Mounting Type | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| Operating Temperature | 0 C to +70 C (commercial) | β |
| RoHS Status | Contains lead / RoHS non-compliant (per Altera listing) | [DATA_NEEDED: RoHS compliance per specific part marking] |
| User I/O Pins | β | 64 |
| Pin-to-Pin Delay (tPD) | β | 20 ns |
| Supply Voltage (VCC) | β | 5.0 V |
| Operating Temperature (Commercial) | β | 0C to +70C |
| Programming Interface | β | IEEE 1149.1 JTAG (ISP) |
| In-System Programmable | β | Yes (5.0-V ISP) |
| Package | β | PLCC-84 (windowed ceramic carrier not applicable - plastic) |
| Technology | β | CMOS EEPROM |
| Global Clock Inputs | β | 4 |
| Logic Element Type | β | EEPROM-based macrocell |