EPM9320ALC84-20 vs EPM9320LI84-20 Comparison
Detailed side-by-side comparison of EPM9320ALC84-20 by Altera and EPM9320LI84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320ALC84-20 | EPM9320LI84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.50 | $12.80 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | β |
| Maximum User I/Os | 212 | β |
| Pin-to-Pin Delay (tPD) | 20 ns | β |
| Package | PLCC-84 | 84-PLCC (J-Lead, plastic LCC) |
| Process Technology | 0.5 Β΅m CMOS EEPROM | High-performance CMOS EEPROM |
| Supply Voltage | 5.0 V | 5.0 V |
| Programmability | In-system via IEEE 1149.1 JTAG | β |
| Operating Temperature | [DATA_NEEDED: commercial or industrial grade] | -40 C to +85 C (industrial) |
| Mounting Type | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket-compatible) |
| Configuration Memory | Non-volatile EEPROM | β |
| Boundary Scan | JTAG IEEE 1149.1 | β |
| Design Software | MAX+PLUS II / Quartus II (legacy) | β |
| RoHS Status | [DATA_NEEDED: per Altera datasheet] | [DATA_NEEDED: RoHS compliance] |
| Manufacturer | β | Altera (acquired by Intel) |
| User I/Os | β | 60 |
| Propagation Delay (tPD) | β | 20 ns |
| Internal Frequency | β | 118 MHz |
| Logic Family | β | CMOS, EEPROM-based |
| Architecture | β | Multiple Array MatriX (MAX) - third generation |
| In-System Programmability | β | Yes (IEEE 1149.1 JTAG) |