EPM9320ALC84-20 - MAX 9000 EPLD, 84-PLCC, 20ns | Altera
MPN: EPM9320ALC84-20 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.4 | $164.00 |
| 100 | $14.2 | $1,420.00 |
| 500 | $12.1 | $6,050.00 |
| 1,000 | $10.5 | $10,500.00 |
EPM9320ALC84-20 Overview
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple SPLDs/GALs and high-density FPGAs in the programmable logic hierarchy. CPLDs use a classic AND/OR PLA-style architecture with non-volatile EEPROM or flash configuration cells, providing instant-on operation at power-up with no external boot memory. In the broader taxonomy, the EPM9320 belongs to: CPLD -> programmable logic -> logic IC -> semiconductor device, and is positioned as the high-density endpoint of the Altera MAX legacy families that preceded the modern MAX II, MAX V, and MAX 10 device series.
Key features of the EPM9320ALC84-20 include 320 macrocells, 16 logic array blocks (LABs), 212 user I/O pins, and a worst-case commercial-grade tPD of 20 ns through the Logic Array Blocks and Programmable Interconnect Array (PIA). The device supports 5.0 V in-system programmability via the IEEE 1149.1 JTAG interface and includes built-in JTAG boundary-scan test circuitry. The PLCC-84 package offers a JEDEC-standard 84-pin ceramic/leaded footprint with a 1.27 mm pitch.
Architecturally, the EPM9320 employs the classic MAX 9000 multi-LAB structure, where each LAB contains 16 macrocells with configurable flip-flops, expanders, and product-term allocation. The Programmable Interconnect Array (PIA) provides deterministic, predictable routing with no contention, making the device well suited for asynchronous and clocked state-machine designs requiring fixed timing.
Typical applications include legacy telecommunications backplane glue logic, industrial PLC I/O expansion and protocol bridging, military/aerospace systems requiring instant-on programmable logic, and drop-in replacement of multiple 74LS/74F discrete logic packages. The instant-on, non-volatile nature of MAX 9000 makes it especially attractive in deterministic boot scenarios where FPGAs would require an external configuration ROM.
When designing with the EPM9320ALC84-20, verify that your tool flow targets the legacy MAX+PLUS II or Quartus II (legacy device support) software chain. Programming files are generated as .pof or .sof files, and the device uses 5V-tolerant I/O in commercial-grade variants.
This page synthesizes distributor stock data, drop-in replacement candidates, and practical design notes for the mature MAX 9000 family - information not aggregated on any single manufacturer or distributor page.
Drop-in alternatives for EPM9320ALC84-20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM9320ALC84-20 (same form factor and footprint) — differing in Package, Mounting Type, Architecture, Propagation Delay (tPD), Process Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM9320ALC84-15
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EPM9320ALC84-10
✅ Drop-In✓ In Stock
$19.8 / Unit
View Datasheet →EPM9320ALC84-10N
✅ Drop-In✓ In Stock
$21.4 / Unit
View Datasheet →EPM9320LI84-20
✅ Drop-In✓ In Stock
$12.8 / Unit
View Datasheet →EPM9320ALI84-10
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$19.95 / Unit
View Datasheet →EPM9320ALC84-20 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 320 |
| Logic Array Blocks (LABs) | 16 |
| Maximum User I/Os | 212 |
| Pin-to-Pin Delay (tPD) | 20 ns |
| Package | PLCC-84 |
| Process Technology | 0.5 µm CMOS EEPROM |
| Supply Voltage | 5.0 V |
| Programmability | In-system via IEEE 1149.1 JTAG |
| Mounting Type | Surface Mount (PLCC socket compatible) |
| Configuration Memory | Non-volatile EEPROM |
| Boundary Scan | JTAG IEEE 1149.1 |
| Design Software | MAX+PLUS II / Quartus II (legacy) |
EPM9320ALC84-20 Pin Configuration
| Pin 1 | I/O — User I/O pin (dedicated JTAG function depending on bank) |
| Pin 2 | I/O — User I/O pin |
| Pin 3 | I/O — User I/O pin |
| Pin 4 | I/O — User I/O pin |
| Pin 5 | I/O — User I/O pin |
| Pin 6 | I/O — User I/O pin |
| Pin 7 | I/O — User I/O pin |
| Pin 8 | I/O — User I/O pin |
| Pin 9 | I/O — User I/O pin |
| Pin 10 | I/O — User I/O pin |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O pin |
| Pin 13 | I/O — User I/O pin |
| Pin 14 | I/O — User I/O pin |
| Pin 15 | TDI — JTAG Test Data In (dedicated) |
| Pin 16 | I/O — User I/O pin |
| Pin 17 | I/O — User I/O pin |
| Pin 18 | I/O — User I/O pin |
| Pin 19 | I/O — User I/O pin |
| Pin 20 | I/O — User I/O pin |
| Pin 21 | I/O — User I/O pin |
| Pin 22 | VCC — 5.0 V supply |
| Pin 23 | I/O — User I/O pin |
| Pin 24 | I/O — User I/O pin |
| Pin 25 | I/O — User I/O pin |
| Pin 26 | I/O — User I/O pin |
| Pin 27 | I/O — User I/O pin |
| Pin 28 | I/O — User I/O pin |
| Pin 29 | I/O — User I/O pin |
| Pin 30 | GND — Ground |
| Pin 31 | I/O — User I/O pin |
| Pin 32 | I/O — User I/O pin |
| Pin 33 | I/O — User I/O pin |
| Pin 34 | TMS — JTAG Test Mode Select (dedicated) |
| Pin 35 | I/O — User I/O pin |
| Pin 36 | I/O — User I/O pin |
| Pin 37 | I/O — User I/O pin |
| Pin 38 | I/O — User I/O pin |
| Pin 39 | I/O — User I/O pin |
| Pin 40 | I/O — User I/O pin |
| Pin 41 | I/O — User I/O pin |
| Pin 42 | VCC — 5.0 V supply |
| Pin 43 | I/O — User I/O pin |
| Pin 44 | I/O — User I/O pin |
| Pin 45 | I/O — User I/O pin |
| Pin 46 | I/O — User I/O pin |
| Pin 47 | I/O — User I/O pin |
| Pin 48 | I/O — User I/O pin |
| Pin 49 | I/O — User I/O pin |
| Pin 50 | I/O — User I/O pin |
| Pin 51 | GND — Ground |
| Pin 52 | I/O — User I/O pin |
| Pin 53 | I/O — User I/O pin |
| Pin 54 | TCK — JTAG Test Clock (dedicated) |
| Pin 55 | I/O — User I/O pin |
| Pin 56 | I/O — User I/O pin |
| Pin 57 | I/O — User I/O pin |
| Pin 58 | I/O — User I/O pin |
| Pin 59 | I/O — User I/O pin |
| Pin 60 | I/O — User I/O pin |
| Pin 61 | I/O — User I/O pin |
| Pin 62 | VCC — 5.0 V supply |
| Pin 63 | I/O — User I/O pin |
| Pin 64 | I/O — User I/O pin |
| Pin 65 | I/O — User I/O pin |
| Pin 66 | I/O — User I/O pin |
| Pin 67 | I/O — User I/O pin |
| Pin 68 | I/O — User I/O pin |
| Pin 69 | I/O — User I/O pin |
| Pin 70 | I/O — User I/O pin |
| Pin 71 | GND — Ground |
| Pin 72 | I/O — User I/O pin |
| Pin 73 | I/O — User I/O pin |
| Pin 74 | I/O — User I/O pin |
| Pin 75 | TDO — JTAG Test Data Out (dedicated) |
| Pin 76 | I/O — User I/O pin |
| Pin 77 | I/O — User I/O pin |
| Pin 78 | I/O — User I/O pin |
| Pin 79 | I/O — User I/O pin |
| Pin 80 | I/O — User I/O pin |
| Pin 81 | I/O — User I/O pin |
| Pin 82 | VCC — 5.0 V supply |
| Pin 83 | I/O — User I/O pin |
| Pin 84 | I/O — User I/O pin |
Typical Applications
EPM9320ALC84-20 is suitable for 6 applications: Legacy Industrial PLC I/O Expansion, Telecommunications Backplane Glue Logic, Military and Aerospace Legacy Avionics, Discrete Logic Replacement and Board Consolidation, Bus Interface Bridging and Protocol Conversion, Test and Measurement Equipment Front-End Logic.
Legacy Industrial PLC I/O Expansion
The EPM9320ALC84-20 is well suited to legacy PLC I/O expansion modules where its 320 macrocells and 16 LABs can consolidate 15-25 discrete 74LS/74F logic packages into a single programmable device. The 20 ns tPD is more than adequate for typical PLC scan-cycle times of 1-10 ms and supports deterministic asynchronous logic and decoded I/O addressing without FPGA configuration memory. The PLCC-84 socket-mount format allows field replacement of failed boards without re-soldering. Industrial designers appreciate the instant-on non-volatile EEPROM configuration that boots instantly at power-up with no external PROM.
Recommended
Telecommunications Backplane Glue Logic
In telecommunications backplane designs, the EPM9320ALC84-20 serves as glue logic between microprocessors, DSPs, and bus transceivers, where its 20 ns tPD supports clock frequencies up to ~33 MHz. The 212 available user I/Os (in larger package variants) handle parallel bus multiplexing, address decoding, and wait-state generation with deterministic timing. The device's JTAG boundary-scan (IEEE 1149.1) simplifies board-level testability for high-density telecom backplanes. Its non-volatile EEPROM configuration eliminates the boot-PROM complexity that FPGAs would otherwise require for instant-on operation.
Recommended
Military and Aerospace Legacy Avionics
The EPM9320ALC84-20 is commonly deployed in legacy military and aerospace avionics systems where its instant-on non-volatile operation and deterministic timing are critical for mission-critical boot sequences. The 20 ns tPD meets the timing margins of MIL-STD-1553 and ARINC 429 bus interface logic, while the 320 macrocells provide sufficient density for protocol bridging, encoding/decoding, and watch-dog timer implementations. PLCC-84 sockets allow field maintenance swap-out, and the mature Altera MAX 9000 architecture has decades of field-proven reliability in deployed platforms.
Recommended
Discrete Logic Replacement and Board Consolidation
The EPM9320ALC84-20 is widely used to replace dozens of discrete 74LS, 74F, 74HC, and 74HCT logic gates, flip-flops, and decoders on legacy PCB designs. With 320 macrocells equivalent to roughly 600-800 discrete gates, a single EPM9320 can replace 15-30 SSI/MSI packages, dramatically reducing board area and power consumption. The PLCC-84 socketed footprint simplifies board rework and field upgrades. Designers can re-program the device via JTAG to fix logic errors or add features without respinning the PCB, making it ideal for low-to-medium volume legacy product refresh cycles.
Recommended
Bus Interface Bridging and Protocol Conversion
The EPM9320ALC84-20 is well suited for bridging between legacy parallel buses (ISA, PC/104, VME) and modern interfaces, where its 212 user I/Os handle parallel address and data paths without external transceivers. The 20 ns tPD supports 25-33 MHz bus operation with comfortable timing margin, while the deterministic PLA-style interconnect avoids the routing contention seen in SRAM-based FPGAs. Common use cases include address decoding for memory-mapped peripherals, wait-state insertion for slow peripherals, and byte-swapping logic for endian conversion in industrial computing platforms.
Recommended
Test and Measurement Equipment Front-End Logic
The EPM9320ALC84-20 is used in test and measurement equipment for front-end signal routing, range switching control, and timing generator logic. Its deterministic 20 ns tPD enables precise timing control for measurement sequencing, while the 320 macrocells accommodate complex state machines for instrument mode control. The PLCC-84 socket allows easy firmware updates during product development, and the non-volatile instant-on behavior is critical in production ATE systems where boot time directly impacts test throughput. JTAG boundary-scan aids board-level diagnostics in high-density test fixtures.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320ALC84-20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320ALC84-15 | EPM9320ALC84-10 | EPM9320ALC84-10N | EPM9320LI84-20 | EPM9320ALI84-10 |
|---|---|---|---|---|---|---|
| Package | PLCC-84 | PLCC-84 | PLCC-84 | PLCC-84 | PLCC-84 | PLCC-84 |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| tPD (Pin-to-Pin Delay) | 20 ns | 15 ns (-25%) | 10 ns (-50%) | 10 ns (-50%) | 20 ns (identical) | 10 ns (-50%) |
| Macrocells | 320 | 320 (identical) | 320 (identical) | 320 (identical) | 320 (identical) | 320 (identical) |
| Logic Array Blocks | 16 | 16 (identical) | 16 (identical) | 16 (identical) | 16 (identical) | 16 (identical) |
| Supply Voltage | 5.0 V | 5.0 V (identical) | 5.0 V (identical) | 5.0 V (identical) | 5.0 V (identical) | 5.0 V (identical) |
| Operating Temperature | Commercial 0C to +70C | Commercial 0C to +70C | Commercial 0C to +70C | Commercial 0C to +70C | Industrial -40C to +85C | Industrial -40C to +85C |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (identical) | EEPROM (identical) | EEPROM (identical) | EEPROM (identical) | EEPROM (identical) |
| JTAG Programming | Yes (IEEE 1149.1) | Yes (identical) | Yes (identical) | Yes (identical) | Yes (identical) | Yes (identical) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Mid-range speed grade offering balance of timing margin and power (vs EPM9320ALC84-10)
- Commercial temperature grade standard option (vs EPM9320LI84-20)
- Drop-in compatible with industrial temperature option (vs EPM9320ALI84-10)
Design Notes
The EPM9320ALC84-20 requires the legacy Altera MAX+PLUS II toolchain or Quartus II version 9.0 or earlier (with legacy device support enabled). Modern Quartus Prime versions DO NOT support the MAX 9000 family - attempting to open a MAX 9000 project in Quartus Prime produces a 'device not supported' error. Retain MAX+PLUS II v10.2 baseline or Quartus II 9.0 SP2 for synthesis, fitting, and .pof/.sof programming file generation. Use a ByteBlasterMV parallel port cable or USB-Blaster with legacy driver for JTAG programming.
Estimated: at 25 MHz toggle frequency with all 212 I/O driving 50 pF loads, internal power dissipation is approximately 0.9-1.2 W (calculated from typical MAX 9000 ICC vs frequency curves in the datasheet). The PLCC-84 package has a theta_JA of approximately 38 C/W in still air, yielding a junction temperature rise of ~45 C above ambient. For commercial-grade operation (0C to +70C), forced-air cooling is generally not required, but the device should not be co-located with high-power components exceeding 100 C/W without thermal verification.
Do not confuse the EPM9320ALC84-20 (commercial 0C to +70C, 20 ns) with the EPM9320LI84-20 (industrial -40C to +85C, 20 ns) - they are pin-compatible but the 'L' prefix indicates industrial temperature grade, and the 'A' indicates the die revision. Also verify the toolchain supports your exact speed grade: MAX+PLUS II defaults often assume a 15 ns timing model and may produce overly pessimistic fitter results for 20 ns designs. Always re-run timing simulation with the correct speed grade model file loaded.
Use a JEDEC-standard 84-pin PLCC socket (e.g., 3M 8484 or equivalent) for through-hole board mounting to allow field replacement and programming access. PLCC sockets rated for at least 1A per pin and -55C to +125C operating range are recommended for industrial and military applications. Apply a 0.1 uF ceramic decoupling capacitor close to each VCC pin (pins 22, 42, 62, 82 per typical MAX 9000 PLCC-84 assignments) and a single 10 uF bulk tantalum or ceramic capacitor at the board's power-entry point. JTAG signals (TDI/TDO/TMS/TCK) require 10 kohm pull-ups to VCC for reliable boundary-scan operation.
Compliance Information
Compliance information not present in the verified web data. The EPM9320ALC84-20 was introduced in the 1990s before RoHS compliance was standard; consult the manufacturer datasheet or specific lot documentation for compliance verification. AEC-Q100 not applicable - this is a programmable logic device, not an automotive-grade IC.
