EPM9320LC84-20 vs EPM9320ALC84-20 Comparison
Detailed side-by-side comparison of EPM9320LC84-20 by Altera and EPM9320ALC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320LC84-20 | EPM9320ALC84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $10.50 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD - Complex Programmable Logic Device | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 320 | 320 |
| User I/Os | 60 | β |
| Logic Family | CMOS (EEPROM-based) | β |
| Package | PLCC-84 (Plastic Leaded Chip Carrier) | PLCC-84 |
| Pins | 84 | β |
| Propagation Delay (tPD) | 16 ns | β |
| Internal Counter Frequency | 118 MHz | β |
| Supply Voltage | 5.0 V | 5.0 V |
| Operating Temperature | 0 C to 70 C | [DATA_NEEDED: commercial or industrial grade] |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | β |
| Dedicated Inputs | 4 (global clock / clear / OE) | β |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | β |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: per Altera datasheet] |
| Logic Array Blocks (LABs) | β | 16 |
| Maximum User I/Os | β | 212 |
| Pin-to-Pin Delay (tPD) | β | 20 ns |
| Process Technology | β | 0.5 Β΅m CMOS EEPROM |
| Programmability | β | In-system via IEEE 1149.1 JTAG |
| Mounting Type | β | Surface Mount (PLCC socket compatible) |
| Configuration Memory | β | Non-volatile EEPROM |
| Boundary Scan | β | JTAG IEEE 1149.1 |
| Design Software | β | MAX+PLUS II / Quartus II (legacy) |