EPM9400RC208-20 vs EPM9560RI208-15N Comparison

Detailed side-by-side comparison of EPM9400RC208-20 by Altera and EPM9560RI208-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM9400RC208-20

EPM9400RC208-20 - MAX 9000 CPLD 400 Macro Cells 20ns | Altera

EPM9400RC208-20 Obsolete
Altera
EPM9560RI208-15N

EPM9560RI208-15N - MAX 9000 EPLD, 208-Pin RQFP, 15ns | Altera

EPM9560RI208-15N Obsolete

Specification Comparison

Parameter EPM9400RC208-20 EPM9560RI208-15N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $60.49 $19.45
Family MAX 9000 β€”
Programmable Type In System Programmable (ISP) β€”
Macro Cells 400 β€”
Usable Gates 8,000 β€”
Pin-to-Pin Propagation Delay 20 ns β€”
Maximum Operating Frequency 100 MHz β€”
Supply Voltage (Internal) 4.75 V to 5.25 V β€”
Configuration Technology EEPROM-based (non-volatile) β€”
JTAG Interface IEEE Std. 1149.1 β€”
Package 208-pin RQFP (28x28 mm) 208-pin RQFP (Ruggedized Quad Flat Pack)
Supplier Device Package 208-RQFP β€”
Mounting Type Surface Mount β€”
Operating Temperature [DATA_NEEDED: operating temperature range] 0C to 70C (Commercial)
Number of I/O Pins [DATA_NEEDED: user I/O count] β€”
RoHS Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
MSL Level [DATA_NEEDED: moisture sensitivity level] β€”
Speed Grade -20 (20 ns) -15
Manufacturer β€” Altera (Intel Programmable Solutions Group)
Device Family β€” MAX 9000
Device Type β€” EPLD (Erasable Programmable Logic Device)
Architecture β€” Multiple Array MatriX (MAX), 3rd generation
Configuration Memory β€” CMOS EEPROM, in-system programmable
Total Pins β€” 356 (per third-party catalog; see _validation_note)
Package Pin Count β€” 208
Terminal Form β€” Gull Wing
Package Code β€” HFQFP
User I/Os β€” 216 (per DigiChip specification; see _validation_note)
Maximum Internal Frequency β€” 145 MHz
Propagation Delay (tPD) β€” 11.4 ns (15 ns speed grade)
Supply Voltage β€” 5.0 V
Temperature Grade β€” Industrial (per Vyrian/Partstack listings)
Logic Family β€” CMOS
Programming Interface β€” IEEE 1149.1 JTAG, 5.0-V in-system

Datasheets & Resources

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