Altera

EPM9560RI208-15N - MAX 9000 EPLD, 208-Pin RQFP, 15ns | Altera

MPN: EPM9560RI208-15N ✗ End of Life

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5.0 V Vdss 208-pin RQFP (Ruggedized Quad Flat Pack) Package 145 MHz Speed CMOS EEPROM, in-system programmable Memory

From $19.45 USD / Unit

MOQ: 1 |

Price updated: 2026-09-13

Volume Pricing

Qty	Unit Price	Extended
1	$38.5	$38.50
10	$33.2	$332.00
100	$27.85	$2,785.00
500	$23.1	$11,550.00
1,000	$19.45	$19,450.00

ℹ️ All prices are in USD

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EPM9560RI208-15N Overview

The Altera EPM9560RI208-15N is a high-performance CMOS EEPROM-based programmable logic device from the MAX 9000 family, built on third-generation Multiple Array MatriX (MAX) architecture. Delivered in a 208-pin RQFP (Ruggedized Quad Flat Pack) package with 5.0-V in-system programmability, the device integrates 216 user I/Os, 356 pins, and a maximum internal frequency of 145 MHz with a propagation delay of 11.4 ns at the -15 speed grade.

An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural density of a PLD with on-chip EEPROM configuration memory. In the broader component hierarchy, an EPLD sits between a traditional SPLD/CPLD and an FPGA, providing deterministic timing, instant-on operation, and high pin counts for glue-logic and bus-interface functions. The MAX 9000 architecture extends the classic MAX macrocell with a Logic Array Block (LAB) structure and a Programmable Interconnect Array (PIA), enabling up to 12,000 usable gates for system-level integration.

Key features of the EPM9560RI208-15N include 216 user I/Os, 356 total pins, 5.0-V in-system programmability via IEEE 1149.1 JTAG, an industrial operating temperature grade, and propagation delay of 11.4 ns (15 ns speed grade). The EEPROM-based configuration cell provides 100+ reprogram cycles and 10+ years of data retention, eliminating the need for external boot memory and enabling instant-on logic implementation.

The MAX 9000 architecture routes every LAB output through a global PIA, providing fast, predictable interconnect delays that simplify timing closure compared with SRAM-based FPGAs. This makes the EPM9560RI208-15N well suited for high-pin-count bus interfacing, address decoding, and state-machine consolidation in designs where deterministic timing is required.

Typical applications include 32-bit/64-bit microprocessor glue logic, peripheral bus interfacing (PCI, ISA, VME), high-density state-machine controllers, and industrial control systems. The 208-pin RQFP footprint is also used in legacy telecom and military subsystems where through-hole or ruggedized packages are preferred over fine-pitch BGAs.

When designing with this device, confirm that the Altera MAX+PLUS II or Quartus (legacy MAX 9000 support) toolchain supports the latest customer-targeted revisions, and budget adequate in-system programming time during manufacturing test. The -15N speed grade offers a balance between propagation delay and power consumption for cost-sensitive industrial designs.

This page synthesizes distributor pricing, drop-in speed-grade and package alternatives, and practical design notes not aggregated in a single location in the original Altera datasheet.

Drop-in alternatives for EPM9560RI208-15N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPM9560RI208-15N (same form factor and footprint) — differing in Package, Operating Temperature, Architecture, In-System Programmability, Usable Gates.

EPM9320RI208-20N

Altera

Package: 208-pin PQFP (Plastic Quad Flat Pack)

In-System Programmability: Yes, 5.0 V ISP via JTAG