EPM9400RC240-20 vs EPM9560RI240-20N Comparison
Detailed side-by-side comparison of EPM9400RC240-20 by Altera and EPM9560RI240-20N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9400RC240-20
EPM9400RC240-20 - 400 MC, 20 ns MAX 9000 CPLD, 240-RQFP | Altera
EPM9400RC240-20 NrndIntel
EPM9560RI240-20N
EPM9560RI240-20N - MAX 9000 CPLD, 560 Macro, 191 I/O | Intel
EPM9560RI240-20N β Last Time BuySpecification Comparison
| Parameter | EPM9400RC240-20 | EPM9560RI240-20N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $23.85 | $195.00 |
| Device Family | MAX 9000 | β |
| Macrocells | 400 | 560 |
| Pin-to-Pin Delay (tPD) | 20 ns | β |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | β |
| Logic Elements / LABs | [DATA_NEEDED: number of LABs] | β |
| Programmable Type | In System Programmable (EEPROM) | β |
| Programming Interface | IEEE Std. 1149.1 JTAG | β |
| Package | 240-RQFP (32x32 mm) with exposed pad | 240-pin Power-enhanced BGA (RI240) |
| Supplier Device Package | 240-RQFP | β |
| Mounting Type | Surface Mount | β |
| Operating Temperature | [DATA_NEEDED: commercial/industrial temp grade] | 0C to +70C (commercial) |
| Technology | CMOS, EEPROM-based | β |
| I/O Count | [DATA_NEEDED: usable I/O count for 240-RQFP] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance per data] | [DATA_NEEDED: RoHS compliance] |
| Architecture | MAX (Multiple Array MatriX) - third generation | Multiple Array MatriX (MAX) - third generation |
| Series | MAX 9000 | β |
| Family | β | MAX 9000 |
| Logic Array Blocks (LABs) | β | 12 |
| User I/Os | β | 191 |
| Maximum Internal Frequency | β | 145 MHz |
| Pin-to-Pin Propagation Delay (tPD) | β | 11.4 ns |
| Logic Family | β | CMOS |
| Process Technology | β | CMOS EEPROM |
| Programmability | β | In-system programmable (ISP) via JTAG (IEEE 1149.1) |
| Core Supply Voltage | β | 5.0 V |
| MultiVolt I/O | β | 5.0 V / 3.3 V compatible |
| Programming Language Support | β | AHDL, VHDL, Verilog HDL |
| Development Tools | β | MAX+PLUS II, Quartus II |