EPM9560RI240-20N - MAX 9000 CPLD, 560 Macro, 191 I/O | Intel
MPN: EPM9560RI240-20N ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $260 | $2,600.00 |
| 50 | $235 | $11,750.00 |
| 100 | $215 | $21,500.00 |
| 500 | $195 | $97,500.00 |
EPM9560RI240-20N Overview
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that uses on-chip EEPROM or flash memory to store the configuration. CPLDs sit in the programmable logic hierarchy between simple PLDs (PALs/GALs) and FPGAs: they offer deterministic timing (fixed propagation delay), instant-on operation (no external boot memory), high drive strength, and a Logic Array Block (LAB) structure connected by a programmable interconnect matrix (PIA). The MAX architecture extends classic CPLD concepts with finer-grained logic elements (macrocells), more flexible I/O, and higher usable density, and the 9000 series is positioned as the high-density tier of that family tree.
Key features of the EPM9560RI240-20N include 560 dedicated macrocells (12 Logic Array Blocks), a maximum internal operating frequency of 145 MHz, 11.4 ns propagation delay through the PIA, multiVolt I/O supporting 5.0-V and 3.3-V mixed-voltage interfaces, and a 5.0-V core supply. The die supports user-configurable I/O standards, in-system programmability via JTAG, and is supported by the legacy Altera MAX+PLUS II and Quartus II design environments. Device power is estimated using Altera's PowerPlay power estimation methodology integrated into those tools.
The MAX architecture uses each macrocell to implement a sum-of-products combinatorial function plus an optional flip-flop, with fast feedback paths to the PIA. Global routing is deterministic, which means designers can compute worst-case timing paths analytically - useful for asynchronous bus bridges, interrupt controllers, and other latency-critical glue logic. The 5.0-V tolerant I/O and strong drive capability allow direct interface to TTL/CMOS buses without external transceivers.
Typical applications include high-performance bus interfacing (PCI, VME, ISA bridges), address decoding and wait-state generation in microprocessor systems, state-machine controllers for industrial and telecom equipment, glue logic for ASIC/FPGA-based designs, and high-pin-count glue logic on VME/cPCI backplanes. The 191 user I/O pins enable direct fan-out to wide memory buses and peripheral banks without additional buffering.
When designing with this device, allocate global clocks carefully - the MAX 9000 has a finite number of global clock pins and LAB-local clock resources. Use the MAX+PLUS II fitter report or Quartus compilation report to verify pin assignments and resource utilization, and respect the 5.0-V VCCIO requirements if mixing with 3.3-V peripherals through level-shifting I/O standards. Decoupling bulk 0.1 uF and 10 uF capacitors should be placed as close as possible to every VCC/VCCIO pin to meet in-system programming noise margins.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, including the same-family EPM9560 speed/pinout variants that share the same 240-pin package footprint.
Drop-in alternatives for EPM9560RI240-20N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM9560RI240-20N (same form factor and footprint) — differing in Package, Operating Temperature, Programming Interface, Macrocells, Device Type.
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EPM9560RI240-20
✅ Drop-In✓ In Stock
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View Datasheet →EPM9560RI240-20C
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$52.1 / Unit
View Datasheet →EPM9560RI240-15N
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View Datasheet →EPM9560RC240-20N
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View Datasheet →EPM9560RC240-20
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$122 / Unit
View Datasheet →EPM9560RC240-20C
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View Datasheet →EPM9480RC240-20
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$8.4 / Unit
View Datasheet →EPM9400RC240-20
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$23.85 / Unit
View Datasheet →EPM9560RI240-20N Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Architecture | Multiple Array MatriX (MAX) - third generation |
| Macrocells | 560 |
| Logic Array Blocks (LABs) | 12 |
| User I/Os | 191 |
| Maximum Internal Frequency | 145 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 11.4 ns |
| Logic Family | CMOS |
| Process Technology | CMOS EEPROM |
| Programmability | In-system programmable (ISP) via JTAG (IEEE 1149.1) |
| Core Supply Voltage | 5.0 V |
| MultiVolt I/O | 5.0 V / 3.3 V compatible |
| Package | 240-pin Power-enhanced BGA (RI240) |
| Operating Temperature | 0C to +70C (commercial) |
| Programming Language Support | AHDL, VHDL, Verilog HDL |
| Development Tools | MAX+PLUS II, Quartus II |
EPM9560RI240-20N 240-pin power-enhanced bga (ri240) Pin Configuration Guide
Pin configuration for EPM9560RI240-20N (240-pin power-enhanced bga (ri240) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RI240-20N.
Refer to the datasheet for full pin configuration.
Typical Applications
EPM9560RI240-20N is suitable for 6 applications: High-Performance Bus Bridging (PCI / VME / ISA), Address Decoding and Wait-State Generation, State-Machine and Industrial Control Logic, Telecom Backplane Glue Logic (cPCI / VME), ASIC / FPGA Companion (Configuration and Control), Legacy System Maintenance and Field Upgrades.
High-Performance Bus Bridging (PCI / VME / ISA)
The EPM9560RI240-20N is well-suited as a bus-bridge device between legacy 5-V buses and modern processors. Its 191 user I/Os allow direct fan-out to 32-bit address buses plus control signals without external transceivers, while the deterministic 11.4 ns pin-to-pin delay simplifies timing closure for synchronous bus protocols. With 560 macrocells, designers can implement full address decoding, wait-state generation, byte-enable logic, and interrupt controllers in a single non-volatile device. Compared to an FPGA-based bridge, the EPM9560RI240-20N eliminates boot PROM and configuration time, providing instant-on operation at power-up.
Recommended
Address Decoding and Wait-State Generation
Classical glue-logic use cases such as address decoding and wait-state generation benefit directly from the EPM9560RI240-20N's deterministic timing and high macrocell count. Each of the 560 macrocells implements a sum-of-products function with an optional flip-flop, so even wide decoders with multiple chip-select outputs and arbitration logic fit on a single device. The 11.4 ns tPD allows the CPLD to be inserted into 33 MHz (30 ns cycle) and lower-speed buses with comfortable timing margins. Industrial and telecom designs favor CPLDs here because designers can re-program in-system via JTAG without removing the part from the board.
Recommended
State-Machine and Industrial Control Logic
The MAX 9000 architecture is well-suited for large state machines, sequencers, and protocol controllers in industrial automation. The EPM9560RI240-20N's 560 macrocells support tens of parallel state machines with extensive I/O for sensor and actuator interfacing, while the non-volatile EEPROM configuration ensures deterministic behavior at every power-up - critical for safety-relevant industrial controllers. The 5.0-V core and MultiVolt I/O allow direct interface to 5-V industrial sensors and 24-V optocoupled inputs through external level shifters. Designers use MAX+PLUS II state-machine entry or VHDL/Verilog synthesis for these applications.
Recommended
Telecom Backplane Glue Logic (cPCI / VME)
CompactPCI and VME backplanes require a high density of glue logic on the system controller and peripheral cards. The EPM9560RI240-20N's 240-pin BGA package offers 191 user I/Os in a footprint that is denser than QFP alternatives and supports the high pin counts required for 64-bit VME or cPCI bus interfacing. The CPLD's instant-on behavior is critical on VME system controllers where bus arbitration must be valid before the main processor boots. The MAX+PLUS II / Quartus II toolchain supports VHDL and Verilog for reusable backplane IP across multiple card designs.
Recommended
ASIC / FPGA Companion (Configuration and Control)
The EPM9560RI240-20N is frequently paired with a host ASIC or FPGA to handle boot configuration, multi-rail sequencing, and peripheral glue that is impractical to integrate into the main device. The CPLD's 5.0-V tolerant I/O can drive legacy peripherals while the host ASIC runs at 3.3 V or 1.8 V. With 560 macrocells, the EPM9560RI240-20N can also implement watchdog timers, interrupt concentrators, and reset distribution for the main processor. Designers appreciate that the CPLD retains its configuration through power cycles, eliminating the need for an external boot PROM.
Recommended
Legacy System Maintenance and Field Upgrades
Because the MAX 9000 family is in last-time-buy status, the EPM9560RI240-20N is most often used to maintain or extend the lifetime of long-lifecycle industrial, aerospace, and defense systems originally designed in the late 1990s and 2000s. In-system programmability via JTAG allows field firmware updates without board removal, and the non-volatile EEPROM configuration means no separate boot PROM is required. Engineers designing replacement boards for these systems value the EPM9560RI240-20N's pin compatibility with other MAX 9000 240-pin variants, allowing direct board swaps without re-layout.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RI240-20N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RI240-20 | EPM9560RI240-20C | EPM9560RI240-15N | EPM9560RC240-20N | EPM9480RC240-20 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 240-pin BGA (RI240) | 240-pin BGA (RI240) | 240-pin BGA (RI240) | 240-pin BGA (RI240) | 240-pin BGA (RC240) | 240-pin BGA (RC240) |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 480 |
| User I/Os | 191 | 191 | 191 | 191 | 191 | 160 |
| Maximum Internal Frequency | 145 MHz | 145 MHz | 145 MHz | 135 MHz | 145 MHz | 145 MHz |
| Propagation Delay (tPD) | 11.4 ns | 11.4 ns | 11.4 ns | ~13 ns | 11.4 ns | 11.4 ns |
| Core Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Architecture / Family | MAX 9000 / CMOS EEPROM | MAX 9000 / CMOS EEPROM | MAX 9000 / CMOS EEPROM | MAX 9000 / CMOS EEPROM | MAX 9000 / CMOS EEPROM (ceramic) | MAX 9000 / CMOS EEPROM |
| Lifecycle Status | last_time_buy | last_time_buy | last_time_buy | last_time_buy | last_time_buy | last_time_buy |
Key Differentiators
- Highest macrocell count in MAX 9000 family (vs EPM9480RC240-20)
- Highest density MAX 9000 in 240-pin BGA (vs EPM9320RI208-20N)
- MultiVolt I/O supports mixed 5V/3.3V designs (vs MAX 7000 family (EPM7256SRI208-10))
Design Notes
The EPM9560RI240-20N core operates from a 5.0 V supply with MultiVolt I/O supporting 3.3 V interfaces. Decouple every VCC and VCCIO pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, and add bulk 10 uF tantalum capacitors at each power-supply entry point to the BGA. In-system programming via JTAG requires stable VCC during configuration - power-rail sequencing should hold the CPLD in reset until the 5.0 V rail reaches regulation within +/-5%.
The 240-pin BGA requires a 4-layer or 6-layer PCB with continuous power and ground planes beneath the device for both power integrity and thermal dissipation. Use the MAX+PLUS II or Quartus II pin planner to assign I/O banks and verify that 5.0 V and 3.3 V VCCIO groups are not mixed on the same bank. Escape routing from the BGA must use via-in-pad or microvia technology for the inner rows; confirm with the PCB fabricator that 0.4 mm or finer pitch is supported.
Route JTAG signals (TCK, TMS, TDI, TDO, TRST) with 50 ohm controlled impedance and a maximum stub length of 10 mm. Keep JTAG traces away from high-speed switching signals to avoid programming failures. Place a 4.7 kohm pull-up on TCK and TDI, and a 4.7 kohm pull-up on TMS - these are required by the IEEE 1149.1 JTAG specification to keep the TAP controller in a defined state during power-up.
Do not assume any EPM9560 package variant is drop-in compatible - the 240-pin (RI240), 208-pin (RI208), and 304-pin (RC304) versions have different I/O counts and pinouts. Verify the specific package code (RI240 in this case) against the board footprint before sourcing substitutes. When migrating an existing design to a faster or slower speed grade (-10/-15/-20), recompile the design in MAX+PLUS II or Quartus II to regenerate the fitter and timing reports - timing constraints must be re-validated for the new tPD and fMAX values.
Compliance Information
RoHS/lead-free status could not be confirmed from the provided web data. The -N suffix in legacy Altera/Intel part numbers often denotes lead-free / RoHS-compliant packaging, but this should be verified against the manufacturer's PCN documentation before use in a RoHS-required design.
