EPM9560GC280-15N vs EPM9560GI280-20 Comparison
Detailed side-by-side comparison of EPM9560GC280-15N by Intel and EPM9560GI280-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560GC280-15N
EPM9560GC280-15N - 560-Macrocell MAX 9000 CPLD, CPGA-280 | Intel
EPM9560GC280-15N NrndIntel
EPM9560GI280-20
EPM9560GI280-20 - 560 Macrocell EE PLD, 280-Pin PGA | Intel/Altera
EPM9560GI280-20 NrndSpecification Comparison
| Parameter | EPM9560GC280-15N | EPM9560GI280-20 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $125.00 | $162.50 |
| Device Family | MAX 9000 | MAX 9000 |
| Product Type | EE PLD / CPLD | β |
| Macrocell Count | 560 | β |
| Usable Gates | 12,000 (typical) | 12,000 |
| Propagation Delay (tPD) | 16.6 ns | β |
| Maximum Clock Frequency | 117.6 MHz | β |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | β |
| Maximum Supply Voltage | 5.25 V | β |
| Logic Technology | CMOS EEPROM | β |
| In-System Programmability | Yes (5.0-V ISP via JTAG) | Yes (IEEE Std. 1149.1 JTAG) |
| Boundary-Scan (JTAG) | IEEE Std. 1149.1 compliant | β |
| Package | CPGA-280 (Ceramic Pin Grid Array, 280 pins) | 280-pin PGA (PIN/PEG, square) |
| Package Code | PGA / CPGA280 | PGA |
| Terminal Form | PIN/PEG | PIN/PEG (through-hole PGA) |
| Operating Temperature Grade | Commercial | β |
| Architecture | Multiple Array MatriX (MAX) 3rd generation | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Technology Node | β | 5.0 V CMOS EEPROM |
| Macrocells | β | 560 |
| Logic Array Blocks (LABs) | β | 28 (16 macrocells each) |
| Maximum User I/O Pins | β | 216 |
| Flip-Flops | β | 772 |
| Pin-to-Pin Delay (Speed Grade) | β | 20 ns |
| Supply Voltage (VCC) | β | 5.0 V |
| Programming Technology | β | EEPROM (non-volatile) |
| Temperature Grade | β | Industrial |
| I/O Pin DC Input Range | β | -0.5 V to VCC + 0.5 V |
| Dedicated-Input Pin DC Input Range | β | -0.3 V to VCC + 0.3 V |
| I/O Transient Envelope (no-load, <20 ns) | β | -2.0 V undershoot to 7.0 V overshoot |
| VCC Ramp Requirement | β | Monotonic rise |
| Development Tool | β | Altera MAX+PLUS II |
| Supported HDLs | β | VHDL, Verilog HDL, AHDL |
| RoHS Status | β | [DATA_NEEDED: RoHS status for GI PGA package] |