EPM9560GI280-20 - 560 Macrocell EE PLD, 280-Pin PGA | Intel/Altera
MPN: EPM9560GI280-20 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $245 | $245.00 |
| 10 | $218.5 | $2,185.00 |
| 100 | $195 | $19,500.00 |
| 250 | $178 | $44,500.00 |
| 500 | $162.5 | $81,250.00 |
EPM9560GI280-20 Overview
A Programmable Logic Device (PLD) is a general-purpose digital integrated circuit whose internal logic and interconnect are defined by the user after manufacturing, allowing one silicon device to implement a wide range of glue logic, state machines, bus interfaces, and datapath controllers. The MAX 9000 family is built on a third-generation Multiple Array MatriX (MAX) architecture that combines fine-grained Logic Array Blocks (LABs) with an EEPROM programming technology, providing non-volatile configuration that retains state across power cycles without an external boot PROM.
Key features of the EPM9560GI280-20 include 12,000 usable gates, 560 macrocells, 216 user I/O pins, 772 flip-flops, an in-system programmability (ISP) interface compliant with IEEE Std. 1149.1 (JTAG), and a 5.0 V VCC core supply. The device is supported by the Altera MAX+PLUS II development system, which offers schematic, VHDL, Verilog HDL, and AHDL design entry together with synthesis, simulation, timing analysis, and device programming.
The MAX 9000 architecture arranges 560 macrocells into 28 LABs of 16 macrocells each, with a continuous FastTrack interconnect running across the chip. Each macrocell contains a programmable-AND/fixed-OR array, an XOR gate for polarity control, a programmable register with clock, clock-enable, clear, and preset controls, and an I/O architecture that supports input, output, output-enable, and bidirectional operation. The result is a flexible platform suitable for high-density glue logic, register-intensive datapaths, and bus-interface bridging.
Typical applications include telecom and datacom line-card glue logic, industrial control and factory automation controllers, military and aerospace avionics, legacy bus-interface bridging, and high-density state-machine replacement of discrete 74LS/74F logic. The non-volatile EEPROM cell array makes it well suited to applications that must boot into a defined state without external configuration memory.
When designing with this device, ensure that the 5.0 V VCC supply rises monotonically and that I/O pin overshoot/undershoot is limited to the datasheet's transient envelope (overshoot to 7.0 V and undershoot to -2.0 V for periods under 20 ns under no-load conditions). Designers should also verify timing closure against the 20 ns speed grade using MAX+PLUS II timing analysis.
This page synthesizes distributor availability, parametric context, and drop-in alternative options for the EPM9560GI280-20 that are not consolidated in the original MAX 9000 datasheet.
Drop-in alternatives for EPM9560GI280-20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM9560GI280-20 (same form factor and footprint) — differing in Package, Architecture, In-System Programmability, Usable Gates, Device Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM9560GI280-15
✅ Drop-In✓ In Stock
$110 / Unit
View Datasheet →EPM9560GC280-20
✅ Drop-In✓ In Stock
$360 / Unit
View Datasheet →EPM9560GC280-20N
✅ Drop-In✓ In Stock
$285 / Unit
View Datasheet →EPM9560GC280-15
✅ Drop-In✓ In Stock
$115 / Unit
View Datasheet →EPM9560GC280-15N
✅ Drop-In✓ In Stock
$125 / Unit
View Datasheet →EPM9560GI280-20 Maximum Ratings & Electrical Characteristics
| Device Family | MAX 9000 |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Technology Node | 5.0 V CMOS EEPROM |
| Macrocells | 560 |
| Logic Array Blocks (LABs) | 28 (16 macrocells each) |
| Usable Gates | 12,000 |
| Maximum User I/O Pins | 216 |
| Flip-Flops | 772 |
| Pin-to-Pin Delay (Speed Grade) | 20 ns |
| Supply Voltage (VCC) | 5.0 V |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) |
| Programming Technology | EEPROM (non-volatile) |
| Package | 280-pin PGA (PIN/PEG, square) |
| Terminal Form | PIN/PEG (through-hole PGA) |
| Package Code | PGA |
| Temperature Grade | Industrial |
| I/O Pin DC Input Range | -0.5 V to VCC + 0.5 V |
| Dedicated-Input Pin DC Input Range | -0.3 V to VCC + 0.3 V |
| I/O Transient Envelope (no-load, <20 ns) | -2.0 V undershoot to 7.0 V overshoot |
| VCC Ramp Requirement | Monotonic rise |
| Development Tool | Altera MAX+PLUS II |
| Supported HDLs | VHDL, Verilog HDL, AHDL |
EPM9560GI280-20 pga Pin Configuration Guide
Pin configuration for EPM9560GI280-20 (pga package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560GI280-20.
Refer to the datasheet for full pin configuration.
Typical Applications
EPM9560GI280-20 is suitable for 6 applications: Telecom Line-Card Glue Logic, Industrial Control and Factory Automation Controllers, Legacy Bus-Interface Bridging, Military and Aerospace Avionics, High-Density State-Machine Replacement of Discrete 74LS/74F Logic, Datacom Switch and Router Fabric Glue.
Telecom Line-Card Glue Logic
The EPM9560GI280-20 fits telecom line-card glue logic because its 560 macrocells, 216 user I/O pins, and 772 flip-flops can absorb the bus-bridging, address-decode, and timing functions historically implemented by dozens of 74LS/74F TTL parts. The 20 ns pin-to-pin delay is well matched to TDM bus timing budgets, and the 5.0 V VCC rail is compatible with legacy line-card backplanes. The non-volatile EEPROM cell array ensures the card boots into a known state without external configuration memory, simplifying hot‑out and warm‑reset scenarios, and the JTAG (IEEE Std. 1149.1) ISP interface allows board-level reprogramming during provisioning. Designers should still verify I/O transient envelope (-2.0 V to 7.0 V for <20 ns) against line-card ESD protection.
Recommended
Industrial Control and Factory Automation Controllers
The EPM9560GI280-20 suits industrial control applications because its industrial temperature grade, ceramic PGA package, and 560-macrocell capacity support encoder decoding, PWM generation, safety interlock logic, and fieldbus glue in PLC and motion-controller designs. The 216 user I/O pins accommodate multi-axis servo loops with generous headroom for parallel encoder and limit-switch wiring, and the 772 flip-flops handle state machines for sequencing axis moves and HMI scans. EEPROM non-volatility preserves the control program across power loss, and the JTAG ISP interface supports field updates on the manufacturing line. Engineers should add external input protection and verify the monotonic VCC ramp requirement is met by the industrial 5 V supply.
Recommended
Legacy Bus-Interface Bridging
The EPM9560GI280-20 is well suited to legacy bus-interface bridging because its 560 macrocells and 772 flip-flops can host multi-protocol state machines (e.g., ISA-to-PCI, VME-to-PCI, or parallel-port-to-memory bridges) with deterministic 20 ns pin-to-pin timing. The 216 user I/O pins accept both 5 V and mixed-voltage buses (with external bus switches), and the 28 LABs of 16 macrocells each deliver balanced logic distribution across the FastTrack interconnect. The 5.0 V VCC supply is directly compatible with TTL/CMOS legacy buses, and the JTAG ISP interface simplifies in-the-field firmware updates. Designers bridging to modern 3.3 V domains should add series resistors or level shifters to protect the 5.0 V I/O cells.
Recommended
Military and Aerospace Avionics
The EPM9560GI280-20 suits military and aerospace avionics because its ceramic PGA (PIN/PEG) package provides the mechanical robustness and hermeticity often required for ruggedized environments, while the industrial temperature grade and 560-macrocell capacity address MIL-STD-454 and MIL-STD-883 inspection profiles. The 12,000 usable gates handle navigation display multiplexing, sensor-fusion glue, and ARINC-429/1553B interface bridging without external logic. The non-volatile EEPROM cell array preserves the mission configuration across power cycles, and the JTAG ISP interface allows board-level BIT (built-in test) reprogramming. Engineers should verify derating against the specific avionics environmental profile and confirm lot acceptance and traceability through authorized aftermarket channels.
Recommended
High-Density State-Machine Replacement of Discrete 74LS/74F Logic
The EPM9560GI280-20 replaces racks of discrete 74LS/74F logic because its 560 macrocells and 772 flip-flops can absorb hundreds of legacy SSI/MSI packages into a single ceramic PGA device, reducing board area, power, and BOM cost. The 216 user I/O pins accept the wide fan-in/fan-out buses typical of retrofits, and the 28 LABs of 16 macrocells each provide an efficient mapping for classic state-machine decomposition. The 5.0 V VCC rail matches the TTL supply directly, and the 20 ns pin-to-pin delay covers the typical 74F propagation budget. The non-volatile EEPROM cell array preserves the design across power cycles, eliminating PROM/PLD battery backup.
Recommended
Datacom Switch and Router Fabric Glue
The EPM9560GI280-20 fits datacom switch and router fabric glue logic because its 560 macrocells can host header-processing state machines, queue-management counters, and fabric-side arbitration while the 216 user I/O pins accommodate parallel datapaths and status buses. The 5.0 V VCC rail matches legacy switch-card power planes, and the 20 ns pin-to-pin delay supports line-rate decisions on lower-speed fabric interfaces. The JTAG ISP interface enables board-level provisioning and field updates, and the EEPROM non-volatility ensures the switch boots into a defined state. Designers should isolate any 3.3 V fabric-side signals with series resistors or level shifters to protect the 5.0 V I/O cells.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560GI280-20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560GI280-15 | EPM9560GC280-20 | EPM9560GC280-20N | EPM9560GC280-15 | EPM9560GC280-15N |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 280-pin PGA (PIN/PEG) | 280-pin PGA (PIN/PEG) - same | 280-pin PGA (PIN/PEG) - same | 280-pin PGA (PIN/PEG) - same | 280-pin PGA (PIN/PEG) - same | 280-pin PGA (PIN/PEG) - same |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 |
| Speed Grade (pin-to-pin delay) | 20 ns | 15 ns | 20 ns | 20 ns | 15 ns | 15 ns |
| Maximum User I/O | 216 | 216 | 216 | 216 | 216 | 216 |
| Flip-Flops | 772 | 772 | 772 | 772 | 772 | 772 |
| Temperature Grade Code | Industrial (I) | Industrial (I) | C-code | C-code, lead-free | C-code | C-code, lead-free |
| Lead-Free Suffix | No (standard) | No (standard) | No (standard) | Yes (N suffix) | No (standard) | Yes (N suffix) |
| In-System Programmability (JTAG) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) |
| Supply Voltage (VCC) | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
Key Differentiators
- Highest-density MAX 9000 in a 280-pin PGA (vs EPM9480RC240-20)
- Non-volatile EEPROM configuration (vs EPM7256SQC208-10)
- JTAG ISP at 5.0 V (vs EPM9560GI280-15)
Design Notes
The MAX 9000 family requires VCC to rise monotonically during power-up; non-monotonic ramps can trigger inadvertent programming or I/O latch-up. According to the Altera datasheet, designers should add a small RC delay or supervisor to enforce monotonicity, and should keep the 5.0 V rail within the datasheet's tolerance before any configuration access is attempted. Decouple VCC with at least one 0.1 uF ceramic capacitor per VCC pin pair plus a single bulk capacitor near the PGA socket.
User I/O pins tolerate transient undershoot to -2.0 V and overshoot to 7.0 V for periods under 20 ns only under no-load conditions. Series resistors (22-33 ohm) on heavily-loaded outputs reduce undershoot/overshoot and dampen transmission-line ringing. According to the Altera datasheet, dedicated input pins have a tighter DC range (-0.3 V to VCC + 0.3 V) and should not be subjected to the same transient envelope as user I/O.
Do not assume the -20 speed grade is interchangeable with the -15 or -10 grade without re-running MAX+PLUS II timing analysis; the 5 ns delta affects state-machine timing closure and bus-bridging margins. Also verify the temperature-grade code ("GI" industrial vs "GC" commercial or "C" code) against the operating environment, and confirm lead-free ("N") suffix compatibility with the assembly process before substituting.
The 280-pin ceramic PGA requires a matching PGA socket with through-hole pin tails on the PCB; allow generous clearance around the socket envelope for the ceramic package body and for inspection access. Pin 1 of the PGA follows the standard JEDEC convention (typically marked by a chamfer or dot on the ceramic lid), and engineers should consult the datasheet pin assignment table before laying out the footprint. Decoupling capacitors should be placed as close as practical to the VCC and GND pin pairs.
Compliance Information
The EPM9560GI280-20 is a legacy ceramic PGA PLD that predates widespread RoHS compliance in the MAX 9000 family; the lead-free 'N' suffix variants (e.g., EPM9560GC280-20N, EPM9560GC280-15N) are the RoHS-compliant drop-in alternatives. AEC-Q100 is not applicable to a PLD in the industrial/aerospace defense usage profile documented in this listing.
