EPM9560GC280-20 vs EPM9320GC280-20 Comparison

Detailed side-by-side comparison of EPM9560GC280-20 by Altera and EPM9320GC280-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560GC280-20 EPM9320GC280-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $360.00 $67.00
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 12,000 6000 (approx.)
Macrocells 560 320
Maximum User I/O 212 β€”
Pin-to-Pin Delay 20 ns (speed grade -20) β€”
Counter Frequency (max) 100 MHz β€”
Supply Voltage (VCCINT) 4.75 V to 5.25 V (5.0 V nominal) β€”
I/O Voltage 3.3 V or 5.0 V configurable β€”
Process Technology CMOS EEPROM β€”
Package 280-pin CPGA (Ceramic Pin Grid Array) 280-pin Ceramic Pin Grid Array (CPGA)
Operating Temperature [DATA_NEEDED: commercial/industrial/military grade] [DATA_NEEDED: operating temperature grade]
In-System Programming Yes, via IEEE 1149.1 JTAG β€”
Mounting Type Through-Hole (CPGA socket) Through-Hole (PGA socket)
RoHS Status [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] unknown
Logic Array Blocks (LABs) β€” 20 (16 macrocells each, typical for MAX 9000)
Maximum Operating Frequency β€” 100 MHz (internal counter)
Propagation Delay (tpd) β€” 23 ns (approx., -20 speed grade)
Supply Voltage (VCC) β€” 4.75 V to 5.25 V (5 V nominal)
Technology β€” CMOS EEPROM
In-System Programmability β€” Yes (5.0-V ISP via JTAG)
JTAG Support β€” IEEE Std. 1149.1 compliant
Configuration Memory β€” EEPROM (non-volatile, instant-on)

Datasheets & Resources

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