EPM9560GC280-20 - MAX 9000 CPLD, 560 Macrocells, 5V, CPGA-280
MPN: EPM9560GC280-20 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $425 | $425.00 |
| 10 | $410 | $4,100.00 |
| 25 | $395 | $9,875.00 |
| 100 | $380 | $38,000.00 |
| 250 | $360 | $90,000.00 |
EPM9560GC280-20 Overview
A CPLD is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL with high-density macrocell arrays, providing deterministic timing, instant-on behavior (no configuration PROM required), and in-system programmability. Within the broader hierarchy, CPLDs sit below FPGAs in density but above simple SPLDs in logic capacity; the MAX 9000 family specifically targets high-density glue-logic, bus-interface, and state-machine applications where predictable timing and ISP via JTAG (IEEE 1149.1) are critical.
Key features include 5.0 V in-system programmability through the built-in JTAG interface, pin-to-pin delays as fast as 10 ns (in faster speed grades), counter speeds up to 144 MHz, and support for both 3.3 V and 5.0 V I/O. The EEPROM-based configuration cell provides non-volatile storage, eliminating the need for an external boot PROM. The high macrocell count and wide I/O count make the EPM9560 suitable for large bus-width interfaces and complex peripheral bridging.
Typical applications include telecommunications infrastructure (T1/E1 framers, line-card glue logic), industrial control (programmable state machines, peripheral bus expansion), military/aerospace systems (where CPGA packaging offers hermeticity and thermal performance), and legacy 5 V system designs requiring high-density logic integration with deterministic timing. The CPGA-280 package also supports through-hole socketed assembly, useful for prototyping and high-reliability military programs.
When designing with this device, ensure adequate decoupling on all VCC pins and follow Altera's JTAG chain recommendations for in-system programming. Designers migrating to newer designs should evaluate MAX II or MAX V CPLDs for lower power, but the EPM9560 remains the preferred choice for existing 5 V systems and long-lifecycle programs where re-qualification is impractical.
Drop-in alternatives for EPM9560GC280-20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM9560GC280-20 (same form factor and footprint) — differing in Package, Architecture, In-System Programmability, Usable Gates, Device Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM9560GC280-15N
✅ Drop-In✓ In Stock
$125 / Unit
View Datasheet →EPM9560GC280-15
✅ Drop-In✓ In Stock
$115 / Unit
View Datasheet →EPM9320GC280-20
✅ Drop-In✓ In Stock
$67 / Unit
View Datasheet →EPM9320GC280-15
✅ Drop-In✓ In Stock
$92.5 / Unit
View Datasheet →EPM9560GC280-20 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 |
| Macrocells | 560 |
| Maximum User I/O | 212 |
| Pin-to-Pin Delay | 20 ns (speed grade -20) |
| Counter Frequency (max) | 100 MHz |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) |
| I/O Voltage | 3.3 V or 5.0 V configurable |
| Process Technology | CMOS EEPROM |
| Package | 280-pin CPGA (Ceramic Pin Grid Array) |
| In-System Programming | Yes, via IEEE 1149.1 JTAG |
| Mounting Type | Through-Hole (CPGA socket) |
EPM9560GC280-20 Pin Configuration
| Pin A1 | I/O — User I/O (specific function per datasheet pinout table) |
| Pin B1 | I/O — User I/O |
| Pin C1 | I/O — User I/O |
| Pin A2 | GND — Ground |
| Pin B2 | VCC — 5.0V core supply |
| Pin A14 | TDI — JTAG Test Data In |
| Pin B14 | TDO — JTAG Test Data Out |
| Pin C14 | TMS — JTAG Test Mode Select |
| Pin D14 | TCK — JTAG Test Clock |
Typical Applications
EPM9560GC280-20 is suitable for 6 applications: Telecommunications Line-Card Glue Logic, Military and Aerospace Avionics Systems, Industrial Control and Factory Automation, Legacy 5V System Design and Refresh, High-Speed Bus Interface Bridging, Medical Imaging Equipment (Legacy Programs).
Telecommunications Line-Card Glue Logic
The EPM9560GC280-20's 560 macrocells and 212 I/O pins make it ideal for high-density glue logic on telecom line cards where multiple bus standards (UTOPIA, H.110, SPI) must be bridged and synchronized. The 100 MHz counter speed and 20 ns pin-to-pin delay support T1/E1 framer interfacing and time-slot assignment without inserting wait states. The JTAG-based ISP allows board-level reprogramming for protocol updates in deployed equipment. The CPGA-280 package offers the hermeticity telecom OEMs require for outdoor cabinet deployments.
Recommended
Military and Aerospace Avionics Systems
The EPM9560GC280-20 in CPGA-280 ceramic packaging is purpose-built for military and aerospace avionics programs that require hermetic sealing, wide operating temperature range, and high reliability. Its 560 macrocells consolidate multiple PAL/GAL devices into a single component, reducing board area and interconnection failure points. The 5V core and 3.3V/5V I/O flexibility interfaces directly to legacy MIL-STD-1553 transceivers and discrete logic. JTAG-ISP enables in-field firmware updates for mission-configurable avionics without removing the unit from service.
Recommended
Industrial Control and Factory Automation
Factory automation PLCs and motor controllers benefit from the EPM9560GC280-20's deterministic timing - CPLD flip-flop propagation is independent of routing, unlike FPGAs, making it ideal for hard-real-time control loops. The 212 I/O support direct connection to parallel ADC/DAC arrays, encoder inputs, and isolated digital I/O modules without intermediate buffering. Industrial -40C to +85C temperature variants handle harsh factory environments. EEPROM-based configuration means instant-on operation after power cycling without boot-time delays.
Recommended
Legacy 5V System Design and Refresh
Designers maintaining existing 5V systems with EOL microcontrollers or peripheral ICs use the EPM9560GC280-20 as a drop-in logic replacement to add new glue functions without redesigning the power architecture. Its native 5V tolerance eliminates level-shifters when interfacing to legacy 5V peripherals. The 560 macrocells absorb functions previously implemented across multiple 22V10 or 32-macrocell CPLDs, simplifying board layout. Obsolescence of legacy PALs makes the EPM9560GC280-20 a popular choice for long-lifecycle defense and medical refresh programs.
Recommended
High-Speed Bus Interface Bridging
The EPM9560GC280-20 bridges disparate bus standards - such as PCI to ISA, VME to local bus, or proprietary backplane protocols - by implementing protocol converters, address decoding, and wait-state generators in a single device. Its 212 user I/O pins accommodate wide parallel buses (32-bit data + 32-bit address + control) without external multiplexing. The 100 MHz counter speed supports bus clock generation, and the deterministic 20 ns pin-to-pin delay simplifies timing closure. JTAG boundary-scan capability verifies interconnect integrity during board bring-up.
Recommended
Medical Imaging Equipment (Legacy Programs)
Long-lifecycle medical imaging equipment such as ultrasound systems, CT scanners, and patient monitors built on 5V architectures use the EPM9560GC280-20 for peripheral timing, beam-former control, and display interface logic. Its deterministic timing is essential for synchronized data acquisition across multiple ADC channels. The CPGA-280 package withstands autoclave sterilization cycles in surgical equipment. FDA-qualified programs rely on the part's mature datasheet and multi-decade Altera manufacturing history for design dossier documentation.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560GC280-20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560GC280-15N | EPM9560GC280-15 | EPM9320GC280-20 | EPM9320GC280-15 |
|---|---|---|---|---|---|
| Package | CPGA-280 | CPGA-280 (same) | CPGA-280 (same) | CPGA-280 (same) | CPGA-280 (same) |
| Brand | Altera | Altera (same) | Altera (same) | Altera (same) | Altera (same) |
| Family | MAX 9000 | MAX 9000 (same) | MAX 9000 (same) | MAX 9000 (same) | MAX 9000 (same) |
| Macrocells | 560 | 560 (same) | 560 (same) | 320 (-43%) | 320 (-43%) |
| Usable Gates | 12,000 | 12,000 (same) | 12,000 (same) | 6,000 (-50%) | 6,000 (-50%) |
| Pin-to-Pin Delay | 20 ns | 15 ns (faster) | 15 ns (faster) | 20 ns (same) | 15 ns (faster) |
| Counter Frequency | 100 MHz | 118 MHz (faster) | 118 MHz (faster) | 100 MHz (same) | 118 MHz (faster) |
| Supply Voltage | 4.75V to 5.25V | 4.75V to 5.25V (same) | 4.75V to 5.25V (same) | 4.75V to 5.25V (same) | 4.75V to 5.25V (same) |
Key Differentiators
- Highest-density MAX 9000 CPLD with 560 macrocells (vs EPM9320GC280-20)
- 12,000 usable gates for high-density glue logic (vs EPM9480RC240-20)
- CPGA-280 ceramic package for hermetic applications (vs EPM9560ARI240-10 (plastic PQFP))
Design Notes
Decouple each VCC pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, plus a bulk 10-100 uF tantalum or polymer capacitor near the device. The CPGA-280 has multiple VCC and GND pins distributed across the array; inadequate decoupling on any one pair can cause supply droop that corrupts JTAG programming. Estimated: at 5V VCC and 200 mA typical active current (MAX 9000 datasheet), each VCC pin supplies approximately 5-10 mA, so distributed decoupling is critical for clean ISP operation.
The CPGA-280 ceramic package has excellent thermal performance (theta_JA approximately 15-20 C/W) compared to plastic equivalents, but still requires attention in high-density designs. Estimated: at 1.5 W maximum power dissipation, junction temperature rises only 23-30 C above ambient. For military temperature grades (-55C to +125C), design conservatively to ensure junction stays below 150 C at maximum rated ambient. Apply thermal compound if mounting to a heat-sinking socket or cold-plate.
The CPGA-280 package requires a through-hole PGA socket or solder-tail pin array on the PCB. Use a machined-pin socket (e.g., 3M Textool or equivalent) for prototyping and field replacement; for production, consider solder directly into plated-through-hole pads for highest reliability. Maintain 0.1 inch (2.54 mm) pitch pin grid with appropriate antipad clearance on inner layers. Route JTAG signals (TCK, TMS, TDI, TDO) away from high-speed I/O to avoid programming interference.
Do not assume all EPM9560GC280-xx variants share identical JTAG IDs - speed-grade and N-suffix variants may have different device IDs that affect programming software chain detection. Always verify the BSDL file matches your exact MPN before running boundary-scan tests. When migrating from -20 to -15 grade, timing analysis must be re-run because hold-time margins change. CPGA packages are sensitive to mechanical shock during handling; use anti-static trays and avoid dropping the device onto hard surfaces.
Compliance Information
CPGA-280 ceramic package historically contains lead in brazed seals; military/aerospace variants typically exempt from RoHS under ceramic exemption. AEC-Q100 not applicable (this is a programmable logic device, not a dedicated automotive IC). Compliance certificates should be requested from distributor.
