EPM9560GC280-20 vs EPM9560GC280-15 Comparison
Detailed side-by-side comparison of EPM9560GC280-20 by Altera and EPM9560GC280-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560GC280-20
EPM9560GC280-20 - MAX 9000 CPLD, 560 Macrocells, 5V, CPGA-280
EPM9560GC280-20 ObsoleteAltera
EPM9560GC280-15
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteSpecification Comparison
| Parameter | EPM9560GC280-20 | EPM9560GC280-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $360.00 | $115.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EE PLD (CMOS EEPROM-based CPLD) |
| Usable Gates | 12,000 | β |
| Macrocells | 560 | β |
| Maximum User I/O | 212 | β |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | β |
| Counter Frequency (max) | 100 MHz | β |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | β |
| I/O Voltage | 3.3 V or 5.0 V configurable | β |
| Process Technology | CMOS EEPROM | β |
| Package | 280-pin CPGA (Ceramic Pin Grid Array) | β |
| Operating Temperature | [DATA_NEEDED: commercial/industrial/military grade] | β |
| In-System Programming | Yes, via IEEE 1149.1 JTAG | β |
| Mounting Type | Through-Hole (CPGA socket) | Through-Hole |
| RoHS Status | [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] | Non-compliant (ceramic CPGA, contains lead) |
| Macro Cells | β | 560 |
| Typical Gates | β | 12,000 |
| Maximum Operating Frequency | β | 117.6 MHz |
| Propagation Delay (tpd) | β | 15 ns (speed grade -15) |
| Propagation Delay (alternate datasheet figure) | β | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | β | 5.0 V |
| Operating Temperature (Commercial) | β | 0C to +70C |
| Package Type | β | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Programmability | β | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| Technology | β | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| Architecture | β | Multiple Array MatriX (MAX) |
| Lifecycle Status | β | Obsolete (legacy Altera MAX 9000 family) |