EPM9560GC280-20 vs EPM9560R1208-20 Comparison

Detailed side-by-side comparison of EPM9560GC280-20 by Altera and EPM9560R1208-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560GC280-20 EPM9560R1208-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $360.00 $22.40
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 12,000 6,000
Macrocells 560 560
Maximum User I/O 212 212
Pin-to-Pin Delay 20 ns (speed grade -20) β€”
Counter Frequency (max) 100 MHz β€”
Supply Voltage (VCCINT) 4.75 V to 5.25 V (5.0 V nominal) β€”
I/O Voltage 3.3 V or 5.0 V configurable β€”
Process Technology CMOS EEPROM CMOS EEPROM, third-generation MAX architecture
Package 280-pin CPGA (Ceramic Pin Grid Array) R-1208 (BGA-style fine-pitch)
Operating Temperature [DATA_NEEDED: commercial/industrial/military grade] 0C to +70C (commercial)
In-System Programming Yes, via IEEE 1149.1 JTAG β€”
Mounting Type Through-Hole (CPGA socket) Surface Mount
RoHS Status [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] [DATA_NEEDED: confirm via current distributor data]
Logic Array Blocks β€” 52 (typical for 560 macrocells)
Propagation Delay (tPD) β€” 20 ns
Maximum Frequency (fMAX) β€” 125 MHz
Supply Voltage (VCCINT/VCCIO) β€” 5.0 V
Technology β€” CMOS EEPROM
In-System Programmability β€” Yes (IEEE 1149.1 JTAG)
Architecture β€” Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA)
Boundary-Scan Test β€” JTAG IEEE Std. 1149.1
Configuration Memory β€” On-chip EEPROM (non-volatile)

Datasheets & Resources

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