EPM9560GI280-20 vs EPM9560GC280-15 Comparison
Detailed side-by-side comparison of EPM9560GI280-20 by Intel and EPM9560GC280-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteSpecification Comparison
| Parameter | EPM9560GI280-20 | EPM9560GC280-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $162.50 | $115.00 |
| Device Family | MAX 9000 | β |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) |
| Technology Node | 5.0 V CMOS EEPROM | β |
| Macrocells | 560 | β |
| Logic Array Blocks (LABs) | 28 (16 macrocells each) | β |
| Usable Gates | 12,000 | β |
| Maximum User I/O Pins | 216 | β |
| Flip-Flops | 772 | β |
| Pin-to-Pin Delay (Speed Grade) | 20 ns | β |
| Supply Voltage (VCC) | 5.0 V | β |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | β |
| Programming Technology | EEPROM (non-volatile) | β |
| Package | 280-pin PGA (PIN/PEG, square) | β |
| Terminal Form | PIN/PEG (through-hole PGA) | β |
| Package Code | PGA | β |
| Temperature Grade | Industrial | β |
| I/O Pin DC Input Range | -0.5 V to VCC + 0.5 V | β |
| Dedicated-Input Pin DC Input Range | -0.3 V to VCC + 0.3 V | β |
| I/O Transient Envelope (no-load, <20 ns) | -2.0 V undershoot to 7.0 V overshoot | β |
| VCC Ramp Requirement | Monotonic rise | β |
| Development Tool | Altera MAX+PLUS II | β |
| Supported HDLs | VHDL, Verilog HDL, AHDL | β |
| RoHS Status | [DATA_NEEDED: RoHS status for GI PGA package] | Non-compliant (ceramic CPGA, contains lead) |
| Family | β | MAX 9000 |
| Device Type | β | EE PLD (CMOS EEPROM-based CPLD) |
| Macro Cells | β | 560 |
| Typical Gates | β | 12,000 |
| Maximum Operating Frequency | β | 117.6 MHz |
| Propagation Delay (tpd) | β | 15 ns (speed grade -15) |
| Propagation Delay (alternate datasheet figure) | β | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | β | 5.0 V |
| Operating Temperature (Commercial) | β | 0C to +70C |
| Package Type | β | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Mounting Type | β | Through-Hole |
| Programmability | β | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| Technology | β | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| Lifecycle Status | β | Obsolete (legacy Altera MAX 9000 family) |