EPM9560GI280-20 vs EPM9560GC280-15N Comparison
Detailed side-by-side comparison of EPM9560GI280-20 by Intel and EPM9560GC280-15N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560GI280-20
EPM9560GI280-20 - 560 Macrocell EE PLD, 280-Pin PGA | Intel/Altera
EPM9560GI280-20 NrndIntel
EPM9560GC280-15N
EPM9560GC280-15N - 560-Macrocell MAX 9000 CPLD, CPGA-280 | Intel
EPM9560GC280-15N NrndSpecification Comparison
| Parameter | EPM9560GI280-20 | EPM9560GC280-15N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $162.50 | $125.00 |
| Device Family | MAX 9000 | MAX 9000 |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) 3rd generation |
| Technology Node | 5.0 V CMOS EEPROM | β |
| Macrocells | 560 | β |
| Logic Array Blocks (LABs) | 28 (16 macrocells each) | β |
| Usable Gates | 12,000 | 12,000 (typical) |
| Maximum User I/O Pins | 216 | β |
| Flip-Flops | 772 | β |
| Pin-to-Pin Delay (Speed Grade) | 20 ns | β |
| Supply Voltage (VCC) | 5.0 V | β |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | Yes (5.0-V ISP via JTAG) |
| Programming Technology | EEPROM (non-volatile) | β |
| Package | 280-pin PGA (PIN/PEG, square) | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Terminal Form | PIN/PEG (through-hole PGA) | PIN/PEG |
| Package Code | PGA | PGA / CPGA280 |
| Temperature Grade | Industrial | β |
| I/O Pin DC Input Range | -0.5 V to VCC + 0.5 V | β |
| Dedicated-Input Pin DC Input Range | -0.3 V to VCC + 0.3 V | β |
| I/O Transient Envelope (no-load, <20 ns) | -2.0 V undershoot to 7.0 V overshoot | β |
| VCC Ramp Requirement | Monotonic rise | β |
| Development Tool | Altera MAX+PLUS II | β |
| Supported HDLs | VHDL, Verilog HDL, AHDL | β |
| RoHS Status | [DATA_NEEDED: RoHS status for GI PGA package] | β |
| Product Type | β | EE PLD / CPLD |
| Macrocell Count | β | 560 |
| Propagation Delay (tPD) | β | 16.6 ns |
| Maximum Clock Frequency | β | 117.6 MHz |
| Supply Voltage (VCCINT/VCCIO) | β | 5.0 V |
| Maximum Supply Voltage | β | 5.25 V |
| Logic Technology | β | CMOS EEPROM |
| Boundary-Scan (JTAG) | β | IEEE Std. 1149.1 compliant |
| Operating Temperature Grade | β | Commercial |