EPM9560GI280-20 vs EPM9560GC280-20N Comparison
Detailed side-by-side comparison of EPM9560GI280-20 by Intel and EPM9560GC280-20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560GI280-20
EPM9560GI280-20 - 560 Macrocell EE PLD, 280-Pin PGA | Intel/Altera
EPM9560GI280-20 NrndAltera
EPM9560GC280-20N
EPM9560GC280-20N - 560 Macrocell MAX 9000 CPLD, 280-Pin CPGA | Altera
EPM9560GC280-20N NrndSpecification Comparison
| Parameter | EPM9560GI280-20 | EPM9560GC280-20N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $162.50 | $285.00 |
| Device Family | MAX 9000 | β |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX), 3rd generation |
| Technology Node | 5.0 V CMOS EEPROM | β |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 28 (16 macrocells each) | β |
| Usable Gates | 12,000 | 6,000 to 12,000 |
| Maximum User I/O Pins | 216 | β |
| Flip-Flops | 772 | β |
| Pin-to-Pin Delay (Speed Grade) | 20 ns | β |
| Supply Voltage (VCC) | 5.0 V | 4.75 V to 5.25 V |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | Yes (5.0-V ISP via IEEE 1149.1 JTAG) |
| Programming Technology | EEPROM (non-volatile) | β |
| Package | 280-pin PGA (PIN/PEG, square) | 280-pin CPGA (Ceramic Pin Grid Array) |
| Terminal Form | PIN/PEG (through-hole PGA) | β |
| Package Code | PGA | β |
| Temperature Grade | Industrial | β |
| I/O Pin DC Input Range | -0.5 V to VCC + 0.5 V | β |
| Dedicated-Input Pin DC Input Range | -0.3 V to VCC + 0.3 V | β |
| I/O Transient Envelope (no-load, <20 ns) | -2.0 V undershoot to 7.0 V overshoot | β |
| VCC Ramp Requirement | Monotonic rise | β |
| Development Tool | Altera MAX+PLUS II | β |
| Supported HDLs | VHDL, Verilog HDL, AHDL | β |
| RoHS Status | [DATA_NEEDED: RoHS status for GI PGA package] | [DATA_NEEDED] |
| Family | β | MAX 9000 |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Technology | β | CMOS EEPROM-based |
| User I/O Pins | β | 212 |
| Pin-to-Pin Delay (tPD) | β | 20 ns |
| Maximum Counter Frequency | β | 144 MHz |
| I/O Voltage | β | 3.3 V or 5 V (configurable) |
| Configuration Memory | β | EEPROM (non-volatile, instant-on) |
| PCI Compliance | β | Yes |
| Operating Temperature | β | [DATA_NEEDED: industrial/commercial grade] |