EPM9560GI280-20 vs EPM9560GI280-15 Comparison
Detailed side-by-side comparison of EPM9560GI280-20 by Intel and EPM9560GI280-15 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560GI280-20
EPM9560GI280-20 - 560 Macrocell EE PLD, 280-Pin PGA | Intel/Altera
EPM9560GI280-20 NrndIntel
EPM9560GI280-15
EPM9560GI280-15 - 560-Macrocell MAX 9000 EPLD, 280-Pin PGA | Intel
EPM9560GI280-15 NrndSpecification Comparison
| Parameter | EPM9560GI280-20 | EPM9560GI280-15 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $162.50 | $110.00 |
| Device Family | MAX 9000 | MAX 9000 |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | CMOS EEPROM, third-generation Multiple Array MatriX (MAX) |
| Technology Node | 5.0 V CMOS EEPROM | β |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 28 (16 macrocells each) | β |
| Usable Gates | 12,000 | β |
| Maximum User I/O Pins | 216 | β |
| Flip-Flops | 772 | 772 |
| Pin-to-Pin Delay (Speed Grade) | 20 ns | β |
| Supply Voltage (VCC) | 5.0 V | β |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | 5.0-V ISP via JTAG |
| Programming Technology | EEPROM (non-volatile) | β |
| Package | 280-pin PGA (PIN/PEG, square) | 280-pin PGA (ceramic, metal-sealed cofired) |
| Terminal Form | PIN/PEG (through-hole PGA) | β |
| Package Code | PGA | β |
| Temperature Grade | Industrial | β |
| I/O Pin DC Input Range | -0.5 V to VCC + 0.5 V | β |
| Dedicated-Input Pin DC Input Range | -0.3 V to VCC + 0.3 V | β |
| I/O Transient Envelope (no-load, <20 ns) | -2.0 V undershoot to 7.0 V overshoot | β |
| VCC Ramp Requirement | Monotonic rise | β |
| Development Tool | Altera MAX+PLUS II | β |
| Supported HDLs | VHDL, Verilog HDL, AHDL | β |
| RoHS Status | [DATA_NEEDED: RoHS status for GI PGA package] | [DATA_NEEDED: RoHS status] |
| User I/Os | β | 216 |
| Dedicated Inputs | β | 12 |
| Logic Elements / Gates | β | 12,000 usable gates |
| Internal Frequency (fMAX) | β | 145 MHz |
| Propagation Delay (tPD) | β | 11.4 ns |
| Clock-to-Output (tCO) | β | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | β | 4.5 V to 5.5 V (3.3 V or 5 V I/O) |
| Operating Temperature | β | -40 Β°C to 85 Β°C (industrial) |
| Process Technology | β | CMOS EEPROM |
| Moisture Sensitivity Level (MSL) | β | MSL-3 (168 hours) |