EPM9560GI280-20 vs EPM9560R1208-20 Comparison
Detailed side-by-side comparison of EPM9560GI280-20 by Intel and EPM9560R1208-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560GI280-20 | EPM9560R1208-20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $162.50 | $22.40 |
| Device Family | MAX 9000 | β |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) |
| Technology Node | 5.0 V CMOS EEPROM | β |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 28 (16 macrocells each) | β |
| Usable Gates | 12,000 | 6,000 |
| Maximum User I/O Pins | 216 | β |
| Flip-Flops | 772 | β |
| Pin-to-Pin Delay (Speed Grade) | 20 ns | β |
| Supply Voltage (VCC) | 5.0 V | β |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | Yes (IEEE 1149.1 JTAG) |
| Programming Technology | EEPROM (non-volatile) | β |
| Package | 280-pin PGA (PIN/PEG, square) | R-1208 (BGA-style fine-pitch) |
| Terminal Form | PIN/PEG (through-hole PGA) | β |
| Package Code | PGA | β |
| Temperature Grade | Industrial | β |
| I/O Pin DC Input Range | -0.5 V to VCC + 0.5 V | β |
| Dedicated-Input Pin DC Input Range | -0.3 V to VCC + 0.3 V | β |
| I/O Transient Envelope (no-load, <20 ns) | -2.0 V undershoot to 7.0 V overshoot | β |
| VCC Ramp Requirement | Monotonic rise | β |
| Development Tool | Altera MAX+PLUS II | β |
| Supported HDLs | VHDL, Verilog HDL, AHDL | β |
| RoHS Status | [DATA_NEEDED: RoHS status for GI PGA package] | [DATA_NEEDED: confirm via current distributor data] |
| Family | β | MAX 9000 |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks | β | 52 (typical for 560 macrocells) |
| Maximum User I/O | β | 212 |
| Propagation Delay (tPD) | β | 20 ns |
| Maximum Frequency (fMAX) | β | 125 MHz |
| Supply Voltage (VCCINT/VCCIO) | β | 5.0 V |
| Technology | β | CMOS EEPROM |
| Operating Temperature | β | 0C to +70C (commercial) |
| Mounting Type | β | Surface Mount |
| Process Technology | β | CMOS EEPROM, third-generation MAX architecture |
| Boundary-Scan Test | β | JTAG IEEE Std. 1149.1 |
| Configuration Memory | β | On-chip EEPROM (non-volatile) |