EPM9560GM280-15 vs EPM9560GI280-20 Comparison
Detailed side-by-side comparison of EPM9560GM280-15 by Altera and EPM9560GI280-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560GM280-15
EPM9560GM280-15 - 560 Macrocells MAX 9000 PLD 5V | Altera
EPM9560GM280-15 NrndIntel
EPM9560GI280-20
EPM9560GI280-20 - 560 Macrocell EE PLD, 280-Pin PGA | Intel/Altera
EPM9560GI280-20 NrndSpecification Comparison
| Parameter | EPM9560GM280-15 | EPM9560GI280-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $110.00 | $162.50 |
| Family | MAX 9000 | β |
| Device Type | EE PLD (EEPROM-based) | β |
| Macrocells | 560 | 560 |
| Flip-Flops | 772 | 772 |
| User I/O | 216 | β |
| Logic Array Blocks (LABs) | 35 (16 macrocells each) | 28 (16 macrocells each) |
| Supply Voltage (Nominal) | 5.0 V | β |
| Supply Voltage (Max) | 5.5 V | β |
| I/O Logic Level Support | 3.3 V or 5 V | β |
| Pin-to-Pin Delay (tPD) | 15 ns (speed grade -15) | β |
| Package | FineLine BGA-280 (GM) | 280-pin PGA (PIN/PEG, square) |
| Process Technology | CMOS EEPROM | β |
| In-System Programmability | Yes (5V ISP via JTAG IEEE 1149.1) | Yes (IEEE Std. 1149.1 JTAG) |
| Operating Temperature | -40C to +85C (industrial) | β |
| RoHS Status | ROHS3 Compliant | [DATA_NEEDED: RoHS status for GI PGA package] |
| MSL Level | 3 (168 Hours) | β |
| Device Family | β | MAX 9000 |
| Architecture | β | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Technology Node | β | 5.0 V CMOS EEPROM |
| Usable Gates | β | 12,000 |
| Maximum User I/O Pins | β | 216 |
| Pin-to-Pin Delay (Speed Grade) | β | 20 ns |
| Supply Voltage (VCC) | β | 5.0 V |
| Programming Technology | β | EEPROM (non-volatile) |
| Terminal Form | β | PIN/PEG (through-hole PGA) |
| Package Code | β | PGA |
| Temperature Grade | β | Industrial |
| I/O Pin DC Input Range | β | -0.5 V to VCC + 0.5 V |
| Dedicated-Input Pin DC Input Range | β | -0.3 V to VCC + 0.3 V |
| I/O Transient Envelope (no-load, <20 ns) | β | -2.0 V undershoot to 7.0 V overshoot |
| VCC Ramp Requirement | β | Monotonic rise |
| Development Tool | β | Altera MAX+PLUS II |
| Supported HDLs | β | VHDL, Verilog HDL, AHDL |