EPM9560RC208-13 vs EPM9560RC208-15C Comparison

Detailed side-by-side comparison of EPM9560RC208-13 by Altera and EPM9560RC208-15C by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RC208-13 EPM9560RC208-15C
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $0.00
Device Family MAX 9000 EPLD β€”
Macrocells 560 560
Usable Gates 12,000 12,000
Logic Array Blocks (LABs) 20 β€”
User I/O Pins 208 149
Package 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP
Package Code RC208 β€”
Speed Grade -13 (13 ns pin-to-pin) -15 (15 ns)
Propagation Delay (tPD) 13 ns 15 ns
Maximum Clock Frequency 125 MHz β€”
Supply Voltage 5.0 V β€”
Configuration Technology EEPROM (non-volatile) β€”
Programming Interface IEEE 1149.1 JTAG β€”
Operating Temperature Range 0C to +70C (commercial) 0C to +70C (commercial)
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Lead-Free Status [DATA_NEEDED: lead-free status] β€”
MSL Level [DATA_NEEDED: MSL level] β€”
Family β€” MAX 9000
Device Type β€” EEPROM-based CPLD (EPLD)
Maximum Counter Frequency β€” 117.6 MHz
Supply Voltage Range β€” 4.75 V to 5.25 V
Nominal Supply Voltage β€” 5.0 V
I/O Voltage Compatibility β€” 3.3 V or 5 V
Configuration Memory β€” EEPROM (non-volatile)
In-System Programmability β€” Yes, via IEEE Std. 1149.1 JTAG
Logic Architecture β€” Multiple Array MatriX (MAX) third generation

Datasheets & Resources

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