EPM9560RC208-15C - MAX 9000 CPLD 560 Macro Cells | Altera
MPN: EPM9560RC208-15C β End of Life| Qty | Unit Price | Extended |
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| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
EPM9560RC208-15C Overview
A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple logic blocks and a programmable interconnect array on a single die, allowing designers to implement custom digital logic without fabricating an ASIC. Within the programmable logic hierarchy, the CPLD sits between simple PLDs and FPGAs: CPLDs offer deterministic timing, non-volatile configuration, and instant-on operation, while FPGAs provide higher gate counts and more flexible routing. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, fabricated on advanced CMOS with EEPROM configuration cells.
Key features include 5.0 V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface, 560 macrocells organized into logic array blocks, and 12,000 usable gates. The EEPROM-based configuration is non-volatile, so the device retains its logic configuration through power cycles without an external configuration memory. The 15 ns speed grade supports counter speeds up to 117.6 MHz, making it suitable for glue logic, bus interfacing, and state machine implementations.
The MAX 9000 architecture uses a programmable interconnect array to route signals between logic array blocks, providing predictable, fixed timing independent of routing. Each macrocell contains a flip-flop and product-term logic, enabling both combinatorial and registered functions. The 149 I/O pins support 3.3 V or 5 V operation, allowing direct interfacing with mixed-voltage systems.
Typical applications include PCI bus interfaces, DSP glue logic, memory controllers, industrial control state machines, and legacy system replacement. The 5 V supply and 5 V-tolerant I/O make the device well suited to retrofitting older 5 V designs where modern low-voltage CPLDs would require level shifting.
When designing with this device, note that the 208-pin RQFP package requires careful PCB layout for the JTAG chain and power decoupling. Because the part is a legacy MAX 9000 device, designers should verify lifecycle availability and consider pin-compatible speed-grade variants for supply continuity.
This page synthesizes distributor pricing, drop-in speed-grade alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for sourcing and designing with the EPM9560RC208-15C.
Drop-in alternatives for EPM9560RC208-15C β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM9560RC208-15C (same form factor and footprint) β differing in Package, Propagation Delay (tPD), Speed Grade, Device Type, Process Technology.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9560RC208-10N
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$175 / Unit
View Datasheet βEPM9560RC208-15
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Contact for price
View Datasheet βEPM9560RC208-14
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$27.9 / Unit
View Datasheet βEPM9560RC208-13
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View Datasheet βEPM9560RC208-12
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View Datasheet βEPM9560RC208-10
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$15.4 / Unit
View Datasheet βEPM9560RC208-15C Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | EEPROM-based CPLD (EPLD) |
| Usable Gates | 12,000 |
| Macrocells | 560 |
| User I/O Pins | 149 |
| Propagation Delay (tPD) | 15 ns |
| Maximum Counter Frequency | 117.6 MHz |
| Supply Voltage Range | 4.75 V to 5.25 V |
| Nominal Supply Voltage | 5.0 V |
| I/O Voltage Compatibility | 3.3 V or 5 V |
| Configuration Memory | EEPROM (non-volatile) |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG |
| Package | 208-pin RQFP |
| Mounting Type | Surface Mount |
| Operating Temperature Range | 0C to +70C (commercial) |
| Speed Grade | -15 (15 ns) |
| Logic Architecture | Multiple Array MatriX (MAX) third generation |
EPM9560RC208-15C 208-pin rqfp Pin Configuration Guide
Pin configuration for EPM9560RC208-15C (208-pin rqfp package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RC208-15C.
Refer to the datasheet for full pin configuration.
Typical Applications
EPM9560RC208-15C is suitable for 6 applications: PCI Bus Interface Glue Logic, Industrial Control State Machines, Legacy 5 V System Replacement, DSP and Processor Glue Logic, Memory Controller and Address Decode, Test and Measurement Instrumentation.
PCI Bus Interface Glue Logic
The EPM9560RC208-15C fits PCI bus interface glue logic because its 15 ns pin-to-pin delay and 117.6 MHz counter speed meet the timing requirements of 33 MHz PCI (30 ns clock period) with margin for combinatorial decode paths. With 560 macrocells and 149 I/O pins, it can implement address decoding, wait-state generation, and interrupt steering in a single device. The 5 V supply and 5 V-tolerant I/O match the legacy PCI signaling environment directly, avoiding level shifters. Placed between the host bridge and peripheral devices, the CPLD adds deterministic, fixed routing delay unlike an FPGA. The trade-off is higher static power than modern low-voltage CPLDs, but for legacy 5 V PCI cards the EPM9560RC208-15C remains a practical single-chip glue solution.
Recommended
Industrial Control State Machines
The EPM9560RC208-15C suits industrial control state machines because its EEPROM configuration is non-volatile and instant-on, so the logic is active within microseconds of power-up without a configuration PROM. The 560 macrocells can implement multiple concurrent state machines, and the 149 I/O pins interface directly with 5 V sensors, relays, and motor drivers common in factory automation. The 15 ns propagation delay provides deterministic response for interlock and safety sequencing. Because the MAX 9000 architecture uses a fixed programmable interconnect array, timing is predictable and does not vary with placement, simplifying worst-case analysis. The main consideration is the 0C to +70C commercial temperature range, which may require an industrial-grade alternative in harsh environments.
Recommended
Legacy 5 V System Replacement
The EPM9560RC208-15C is used to replace failed or obsolete CPLDs in legacy 5 V systems because it retains the original MAX 9000 architecture, 208-pin RQFP footprint, and 5 V supply, allowing board-level repair without redesign. Its 12,000 usable gates and 560 macrocells match the original EPM9560 logic capacity, so existing JEDEC programming files remain compatible. The built-in IEEE Std. 1149.1 JTAG interface allows in-system reprogramming on the assembled board. Because the device is itself obsolete, repair programs should stock pin-compatible speed grades such as the EPM9560RC208-10N as substitutes. The key benefit is avoiding a costly PCB respin for a single failed logic device in long-lifecycle equipment.
Recommended
DSP and Processor Glue Logic
The EPM9560RC208-15C serves as glue logic around DSPs and processors, implementing chip-select decoding, bus arbitration, and handshake sequencing. Its 149 I/O pins can interface a 32-bit processor bus plus peripheral control lines, while the 560 macrocells absorb address decode and wait-state logic that would otherwise require discrete 74-series devices. The 15 ns propagation delay keeps combinatorial decode within a single processor bus cycle at typical clock rates. Because configuration is stored in EEPROM, the glue logic is available immediately at power-up, before a processor finishes boot. The 5 V I/O matches legacy DSP interfaces directly. Designers should account for the fixed interconnect delay when budgeting bus timing margins.
Recommended
Memory Controller and Address Decode
The EPM9560RC208-15C implements memory controllers and address decode logic because its 560 macrocells can generate chip-selects, refresh timing, and bank switching for SRAM, DRAM, and flash arrays. The 117.6 MHz counter frequency supports refresh counters and wait-state generators, while the 15 ns pin-to-pin delay keeps address decode within a memory access cycle. The 149 I/O pins accommodate wide address and data buses. Non-volatile EEPROM configuration means the controller logic is active at power-up, critical for boot memory initialization. The fixed MAX 9000 interconnect provides predictable timing, simplifying memory timing closure. The trade-off versus a modern CPLD is higher power and a larger 208-pin RQFP footprint.
Recommended
Test and Measurement Instrumentation
The EPM9560RC208-15C is used in test and measurement instrumentation for trigger logic, timing generation, and interface control. Its 15 ns propagation delay and 117.6 MHz counter speed support event detection and pulse generation with nanosecond resolution, while the 560 macrocells implement multiple trigger state machines. The 149 I/O pins interface with front-end ADCs, DACs, and digital I/O. Non-volatile EEPROM configuration ensures the instrument logic is ready immediately at power-on, important for calibration and self-test routines. The 5 V I/O matches legacy instrument backplanes. Because the device is obsolete, instrument manufacturers should qualify pin-compatible speed grades such as the EPM9560RC208-10N to maintain long-term serviceability of installed equipment.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC208-15C β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC208-10N | EPM9560RC208-15 | EPM9560RC208-14 | EPM9560RC208-13 |
|---|---|---|---|---|---|
| Package | 208-pin RQFP | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Brand | Altera | Altera | Altera | Altera | Altera |
| Propagation Delay (tPD) | 15 ns | 10 ns | 15 ns | 14 ns | 13 ns |
| Macrocells | 560 | 560 | 560 | 560 | 560 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| User I/O Pins | 149 | 149 | 149 | 149 | 149 |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) |
| JTAG ISP | Yes (IEEE Std. 1149.1) | Yes (IEEE Std. 1149.1) | Yes (IEEE Std. 1149.1) | Yes (IEEE Std. 1149.1) | Yes (IEEE Std. 1149.1) |
Key Differentiators
- Non-volatile EEPROM configuration with instant-on operation (vs EPM9560RC208-10N)
- 5 V supply with 3.3 V/5 V I/O compatibility (vs EPM9560RC208-10N)
- Deterministic fixed interconnect timing (vs EPM9560RC208-14)
- 149 user I/O pins in a 208-pin RQFP (vs EPM9560RC208-13)
Design Notes
Decouple every VCC pin of the EPM9560RC208-15C with a 0.1 uF ceramic capacitor placed as close to the pin as possible, plus at least one 10 uF bulk capacitor per power plane. The MAX 9000 family draws significant transient current during logic switching at 5 V; inadequate decoupling causes ground bounce and false switching. Estimated: at 117.6 MHz counter operation with 149 I/O switching, transient currents can exceed several hundred milliamps, so use a low-inductance power plane rather than narrow traces.
Route the JTAG chain (TCK, TMS, TDI, TDO) as short, matched traces with a continuous ground reference, and keep TCK away from high-speed I/O to avoid clock noise coupling into the programming interface. Terminate TDO with a series resistor if the trace exceeds a few centimeters. The 208-pin RQFP package requires a fine-pitch land pattern; verify solder mask and paste aperture dimensions against the manufacturer's recommended footprint to avoid bridging.
Do not assume the EPM9560RC208-15C is still in production. It is an obsolete MAX 9000 device, so verify distributor stock and authenticity before committing to a design. Counterfeit and re-marked parts are common for obsolete CPLDs. Also confirm the temperature grade: the C suffix denotes commercial 0C to +70C operation, which is unsuitable for industrial or automotive environments without derating or an alternative grade.
The MAX 9000 architecture provides deterministic, fixed interconnect delay, which simplifies timing analysis, but the 5 V output swing produces fast edges that can cause ringing on long traces. Add series termination resistors (typically 22 to 33 ohm) on high-speed outputs driving traces longer than 5 cm. Keep the programmable interconnect utilization below 100% to leave routing headroom and reduce congestion-related delay.
Compliance Information
RoHS, REACH, lead-free, and halogen-free status are not confirmed in the available distributor data as of 2026-09-13. The MAX 9000 family predates widespread RoHS adoption; request a compliance certificate from the distributor before purchasing for regulated markets.
