EPM9560RC208-15C vs EPM9560RC208-15 Comparison
Detailed side-by-side comparison of EPM9560RC208-15C by Altera and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560RC208-15C
EPM9560RC208-15C - MAX 9000 CPLD 560 Macro Cells | Altera
EPM9560RC208-15C ObsoleteAltera
EPM9560RC208-15
EPM9560RC208-15 - MAX 9000 CPLD 560 Macro Cells 5V | Altera
EPM9560RC208-15 ObsoleteSpecification Comparison
| Parameter | EPM9560RC208-15C | EPM9560RC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $0.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based CPLD (EPLD) | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Usable Gates | 12,000 | 12,000 gates |
| Macrocells | 560 | β |
| User I/O Pins | 149 | β |
| Propagation Delay (tPD) | 15 ns | β |
| Maximum Counter Frequency | 117.6 MHz | β |
| Supply Voltage Range | 4.75 V to 5.25 V | β |
| Nominal Supply Voltage | 5.0 V | β |
| I/O Voltage Compatibility | 3.3 V or 5 V | β |
| Configuration Memory | EEPROM (non-volatile) | β |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes, via IEEE Std. 1149.1 JTAG |
| Package | 208-pin RQFP | 208-pin RQFP (Power Quad Flat Pack) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature Range | 0C to +70C (commercial) | β |
| Speed Grade | -15 (15 ns) | -15 (15 ns pin-to-pin) |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Logic Architecture | Multiple Array MatriX (MAX) third generation | β |
| Macro Cells | β | 560 macro cells |
| Pin-to-Pin Delay | β | 15 ns |
| Counter Speed | β | 117.6 MHz |
| Supply Voltage | β | 5.0 V |
| Configuration Technology | β | EEPROM (non-volatile) |
| Operating Temperature | β | [DATA_NEEDED: operating temperature range] |
| Number of I/O Pins | β | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | β | [DATA_NEEDED: number of logic array blocks] |
| Architecture | β | Third-generation Multiple Array MatriX (MAX) |