EPM9560RC208-19 vs EPM9560RC208-15C Comparison
Detailed side-by-side comparison of EPM9560RC208-19 by Altera and EPM9560RC208-15C by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560RC208-19
EPM9560RC208-19 - MAX 9000 CPLD, 560 Macrocells, 19ns | Altera
EPM9560RC208-19 ObsoleteAltera
EPM9560RC208-15C
EPM9560RC208-15C - MAX 9000 CPLD 560 Macro Cells | Altera
EPM9560RC208-15C ObsoleteSpecification Comparison
| Parameter | EPM9560RC208-19 | EPM9560RC208-15C |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.20 | $0.00 |
| Device Family | MAX 9000 | β |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 12,000 |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | β |
| Flip-Flops | 772 | β |
| User I/O Pins | 149 | 149 |
| Propagation Delay (tPD) | 19 ns | 15 ns |
| Maximum Frequency | [DATA_NEEDED: fMAX] | β |
| Supply Voltage (VCCINT) | 5.0 V | β |
| I/O Voltage Tolerance | 3.3 V / 5 V | β |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | Yes, via IEEE Std. 1149.1 JTAG |
| Technology | CMOS EEPROM | β |
| Package | RQFP-208 (208-pin PQFP) | 208-pin RQFP |
| JEDEC Package Code | S-PQFP-G208 | β |
| Operating Temperature | [DATA_NEEDED: operating temperature grade] | β |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Family | β | MAX 9000 |
| Device Type | β | EEPROM-based CPLD (EPLD) |
| Maximum Counter Frequency | β | 117.6 MHz |
| Supply Voltage Range | β | 4.75 V to 5.25 V |
| Nominal Supply Voltage | β | 5.0 V |
| I/O Voltage Compatibility | β | 3.3 V or 5 V |
| Configuration Memory | β | EEPROM (non-volatile) |
| Operating Temperature Range | β | 0C to +70C (commercial) |
| Speed Grade | β | -15 (15 ns) |
| Logic Architecture | β | Multiple Array MatriX (MAX) third generation |