EPM9560RC208-7 vs EPM9480RC208-15 Comparison

Detailed side-by-side comparison of EPM9560RC208-7 by Altera and EPM9480RC208-15 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RC208-7 EPM9480RC208-15
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $18.90 $24.95
Family MAX 9000 MAX 9000
Device Type EPLD / CPLD β€”
Usable Gates 560 10,000 gates
Macrocells 16 β€”
Logic Array Blocks (LABs) 4 β€”
User I/O Pins 208 153
Pin-to-Pin Delay (tPD) 7 ns (speed grade -7) β€”
Maximum Frequency (fMAX) [DATA_NEEDED: fMAX value] β€”
Supply Voltage (VCCINT) 5.0 V β€”
Supply Voltage (VCCIO) 5.0 V (TTL) or 3.3 V (LVCMOS with level translator) β€”
Process Technology 0.65 um CMOS EEPROM β€”
Configuration Memory Non-volatile on-chip EEPROM (no boot PROM required) EEPROM (non-volatile)
Programming Interface JTAG (IEEE 1149.1) + Altera ISP β€”
Package 208-pin Power Quad Flat Pack (RQFP-208) RQFP-208
Operating Temperature 0C to +70C (commercial) / -40C to +85C (industrial) -40C to +85C (commercial)
Output Drive Current 160 mA DC sink per pin β€”
RoHS Status Compliant (ROHS3 per distributor listing) [DATA_NEEDED: RoHS compliance status]
Logic Cells / Macro Cells β€” 480 macro cells
Maximum Operating Frequency β€” 117.6 MHz
Propagation Delay (tPD) β€” 15 ns
Supply Voltage β€” 5.0 V
Programmability β€” In-System (ISP) via JTAG IEEE 1149.1
Mounting Type β€” Surface Mount
Architecture β€” Multiple Array MatriX (MAX) - 3rd generation
MSL Level β€” [DATA_NEEDED: MSL rating]

Datasheets & Resources

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