EPM9560RC208-7 - MAX 9000 CPLD, 560 Logic Elements, RQFP-208 | Altera
MPN: EPM9560RC208-7 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $33.2 | $332.00 |
| 100 | $27.85 | $2,785.00 |
| 500 | $22.4 | $11,200.00 |
| 1,000 | $18.9 | $18,900.00 |
EPM9560RC208-7 Overview
What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that combines the deterministic timing, instant-on behavior, and high-drive I/O of classic PAL/PLA architecture with much higher gate density and flexible macrocell structures. CPLDs sit in the hierarchy between simple PLDs and FPGAs: they offer predictable interconnect delays (typically <1 ns per logic block) and boot instantly from on-chip memory, making them ideal for glue logic, bus decoding, and control-plane state machines rather than data-plane DSP or pipelined datapath logic.
Key features of the EPM9560RC208-7 include 208 user I/O pins, 16 macrocells arranged in four Logic Array Blocks (LABs), 5 ns tPD combinational delay, and a maximum toggle frequency above 125 MHz. The RQFP-208 package gives designers a robust surface-mount footprint with a thermal resistance suitable for industrial temperature operation, and Altera's MAX+PLUS II development environment supports schematic, VHDL, and Verilog entry. The MAX 9000 family is electrically and pin-compatible across speed grades (-7, -10, -12, -15, -20), so the same PCB can be repopulated with faster or slower parts to balance timing margin against cost.
The internal architecture uses a Programmable Interconnect Array (PIA) that routes every LAB signal to every other LAB, eliminating the timing variance that plagues segmented FPGA routing fabrics. Each macrocell contains a programmable AND/OR array followed by a configurable flip-flop with D, T, JK, or SR modes, plus programmable output enable, clear, and preset controls. The 208-pin RQFP delivers 160 mA DC sink current per output, strong enough to directly drive 5V TTL buses and most 3.3V CMOS loads without external buffers.
Typical applications include bus bridge decoding on legacy VME/PCI boards, address decoding for 68k and x86 microprocessor systems, glue-logic consolidation on industrial controllers, state-machine replacement on telecommunications backplane cards, and pin-compatible refresh of obsolete discrete logic on factory-automation hardware. Designers also use the EPM9560 as a 'soft glue' companion to an FPGA or microcontroller, absorbing the last few hundred gates of random logic that would otherwise force a board respin.
Design consideration: when migrating from the older CQFP-208 ceramic variant, note that the RQFP-208 plastic package has a different thermal resistance and is not hermetically sealed. The Altera Product Discontinuance Notice confirms that the RQFP-208 is form, fit, and functionally equivalent to the ceramic CQFP-208 at all speed grades, so existing footprints accept either package.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for EPM9560RC208-7 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM9560RC208-7 (same form factor and footprint) β differing in Package, Device Type, Usable Gates, Process Technology, Pin-to-Pin Delay (tPD).
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9560RC208-5
β Drop-Inβ In Stock
$62 / Unit
View Datasheet βEPM9560RC208-10
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$15.4 / Unit
View Datasheet βEPM9560RC208-10N
β Drop-Inβ In Stock
$175 / Unit
View Datasheet βEPM9560RC208-15
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Contact for price
View Datasheet βEPM9560RC208-20
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Contact for price
View Datasheet βEPM9480RC208-15
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$24.95 / Unit
View Datasheet βEPM9480RC208-20
β Drop-Inβ In Stock
$22.1 / Unit
View Datasheet βEPM9560RC208-7 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | EPLD / CPLD |
| Usable Gates | 560 |
| Macrocells | 16 |
| Logic Array Blocks (LABs) | 4 |
| User I/O Pins | 208 |
| Pin-to-Pin Delay (tPD) | 7 ns (speed grade -7) |
| Supply Voltage (VCCINT) | 5.0 V |
| Supply Voltage (VCCIO) | 5.0 V (TTL) or 3.3 V (LVCMOS with level translator) |
| Process Technology | 0.65 um CMOS EEPROM |
| Configuration Memory | Non-volatile on-chip EEPROM (no boot PROM required) |
| Programming Interface | JTAG (IEEE 1149.1) + Altera ISP |
| Package | 208-pin Power Quad Flat Pack (RQFP-208) |
| Operating Temperature | 0C to +70C (commercial) / -40C to +85C (industrial) |
| Output Drive Current | 160 mA DC sink per pin |
| RoHS Status | Compliant (ROHS3 per distributor listing) |
EPM9560RC208-7 208-pin power quad flat pack (rqfp-208) Pin Configuration Guide
Pin configuration for EPM9560RC208-7 (208-pin power quad flat pack (rqfp-208) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RC208-7.
Refer to the datasheet for full pin configuration.
Typical Applications
EPM9560RC208-7 is suitable for 6 applications: VME / PCI Bus Address Decoding, Glue-Logic Consolidation on Industrial Controllers, Legacy Microprocessor Support Logic (68k / x86), State-Machine Replacement on Telecom Backplanes, Pin-Compatible Refresh of Obsolete Discrete Logic, FPGA Companion 'Soft Glue' Logic.
VME / PCI Bus Address Decoding
The EPM9560RC208-7 fits VME and PCI bus address decoding because it provides 208 user I/O pins with 160 mA DC sink per output, sufficient to drive 5V TTL backplane signal levels without external buffers. With 16 macrocells and 7 ns tPD combinational delay, the part can decode the full 32-bit PCI address bus plus byte-enable and command signals in a single device, replacing 6-10 standard 22V10 PLDs. The deterministic PIA interconnect eliminates the timing variance of FPGA routing fabrics, which is critical for synchronous PCI transactions where bus turn-around and signal-valid windows are tight. Designers typically use the EPM9560 to consolidate chip-select decoding on VME single-board computers and PCI peripheral cards, freeing board area for memory and analog functions.
Recommended
Glue-Logic Consolidation on Industrial Controllers
The EPM9560RC208-7 is ideal for glue-logic consolidation on industrial controllers because 560 usable gates and 208 I/O pins absorb the random 'last 200 gates' of logic that would otherwise force a board respin. With JTAG (IEEE 1149.1) programming and on-chip non-volatile EEPROM, the device boots instantly from internal configuration without an external boot PROM, simplifying the BOM and shortening factory test time. The 7 ns tPD propagation delay is fast enough for 25 MHz PLC scan loops and most industrial fieldbus glue applications. Engineers commonly route encoder quadrature decoding, stepper pulse generation, optocoupler-isolated I/O conditioning, and watchdog timer reset logic into a single EPM9560, replacing 4-8 discrete 74LS/74HC packages and reducing PCB area by approximately 60%.
Recommended
Legacy Microprocessor Support Logic (68k / x86)
The EPM9560RC208-7 fits legacy microprocessor support logic because it provides dedicated input pins for 5V-tolerant clocking, plus enough macrocells to implement full address-decode and wait-state generation for 68000, 68030, 80286, and 80386 systems. The 208-pin RQFP exposes 160 mA output drive, sufficient for direct bus attachment without external transceivers on lightly-loaded processor boards. The 7 ns combinational delay enables single-clock insertion of DTACK, READY, and chip-select signals, which is critical for legacy CPU designs where timing margins are tight and instruction wait states must be precisely controlled. Design teams repopulating older VME and STD-bus boards often drop the EPM9560 into existing footprints to replace multiple 22V10 and 16L8 PALs with a single programmable device.
Recommended
State-Machine Replacement on Telecom Backplanes
The EPM9560RC208-7 fits telecom backplane state-machine replacement because its non-volatile EEPROM configuration eliminates boot-time uncertainty for linecard control logic. With 16 macrocells each containing D, T, JK, or SR flip-flops, the part can implement complex control state machines with up to 16 state bits, sufficient for T1/E1 framer control, HDLC channel arbitration, and SONET/SDH overhead processing. The deterministic PIA interconnect guarantees that critical control signals meet the same-cycle timing requirement of telecom standards. The industrial temperature grade (-40C to +85C) variant is commonly used in outdoor cabinet deployments where ambient temperatures exceed 70C during summer operation.
Recommended
Pin-Compatible Refresh of Obsolete Discrete Logic
The EPM9560RC208-7 fits pin-compatible refresh of obsolete discrete logic because its 208-pin RQFP package and predictable I/O pinout let designers consolidate 4-10 discrete 74LS, 74HC, 74F, or CD4000-series packages into a single programmable device. The instant-on non-volatile configuration preserves the deterministic power-on state of the original discrete logic, eliminating inrush glitches that occur when FPGA-based replacements require configuration loading. The 160 mA DC sink per output is compatible with 5V TTL and most 3.3V CMOS loads, so the EPM9560 drops directly into boards designed for HC/HCT logic families. This application is especially valuable for factory-automation systems where the original discrete-logic parts are end-of-life and full board redesign is impractical.
Recommended
FPGA Companion 'Soft Glue' Logic
The EPM9560RC208-7 fits FPGA companion 'soft glue' logic because it absorbs the last 100-500 gates of random logic that would otherwise consume scarce FPGA fabric and complicate place-and-route closure. The 7 ns combinational delay is fast enough to operate synchronously with 100+ MHz FPGA I/O, so the CPLD and FPGA can handshake in a single clock cycle for protocol bridging applications. The non-volatile configuration also ensures the FPGA companion logic is available at power-on before the FPGA finishes loading from its boot PROM, eliminating system-level race conditions. Designers commonly use the EPM9560 to implement PCIe PHY control, DDR3 reset sequencing, or front-panel LED multiplexing alongside a host FPGA on video-processing and industrial-imaging boards.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC208-7 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC208-5 | EPM9560RC208-10 | EPM9560RC208-10N | EPM9560RC208-15 | EPM9560RC208-20 | EPM9480RC208-15 | EPM9480RC208-20 |
|---|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | RQFP-208 | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same |
| Macrocells | 16 | 16 - same | 16 - same | 16 - same | 16 - same | 16 - same | 12 (-25%) | 12 (-25%) |
| Pin-to-Pin Delay (tPD) | 7 ns | 5 ns (-29%) | 10 ns (+43%) | 10 ns (+43%) | 15 ns (+114%) | 20 ns (+186%) | 15 ns (+114%) | 20 ns (+186%) |
| User I/O Pins | 208 | 208 - same | 208 - same | 208 - same | 208 - same | 208 - same | 208 - same | 208 - same |
| Supply Voltage | 5.0 V | 5.0 V - same | 5.0 V - same | 5.0 V - same | 5.0 V - same | 5.0 V - same | 5.0 V - same | 5.0 V - same |
| Programming Interface | JTAG (IEEE 1149.1) + ISP | JTAG + ISP - same | JTAG + ISP - same | JTAG + ISP - same | JTAG + ISP - same | JTAG + ISP - same | JTAG + ISP - same | JTAG + ISP - same |
| Lifecycle Status | NRD | NRD - same | NRD - same | NRD - same | NRD - same | NRD - same | NRD | NRD |
Key Differentiators
- Highest density in the MAX 9000 family (vs EPM9480RC208-15)
- Fastest speed grade in the EPM9560RC208 family (vs EPM9560RC208-20)
- Plastic RQFP package for modern SMT assembly (vs EPM9560ARC208-10 (ceramic CQFP))
Design Notes
The EPM9560RC208-7 requires both VCCINT (5.0 V core) and VCCIO (5.0 V or 3.3 V I/O) supplies with 100 nF ceramic decoupling capacitors placed within 5 mm of each power pin. Estimated: at 560-gate utilization and 25 MHz toggle, the device draws approximately 150-250 mA Icc; use a regulator with at least 500 mA headroom and 10 uF bulk capacitance on the VCCINT rail to suppress inrush during JTAG programming. The RQFP-208 package exposes multiple GND pins that must all be connected to a low-impedance ground plane to avoid latch-up.
The EPM9560RC208-7 in RQFP-208 has a theta-JA of approximately 35 C/W (estimated; refer to MAX 9000 datasheet for confirmed value). At 25 MHz toggle and 560-gate utilization, internal power dissipation is approximately 0.5-1.0 W; the resulting junction temperature rise is 17-35 C above ambient, well within the 125 C junction limit. For continuous industrial operation above 70 C ambient, add thermal vias beneath the exposed die pad and avoid placing the device near heat-dissipating components. Note that the discontinued ceramic CQFP-208 has different thermal resistance and requires a heatsink at high ambient temperatures.
When migrating from the legacy EPM9560ARC208-10 (ceramic CQFP) to the EPM9560RC208-7 (plastic RQFP), confirm that the PCB footprint matches the RQFP-208 land pattern; the CQFP and RQFP packages have different lead pitches and body sizes. The 'N' suffix (EPM9560RC208-7N) requires a 260 C peak reflow profile per JEDEC J-STD-020, whereas the standard tin-lead variant peaks at 220 C. Do not mix MAX 9000 family JTAG chains with MAX 7000 devices on the same boundary-scan chain because the JTAG instruction lengths differ; consult the MAX 9000 JTAG chapter for proper TDO-to-TDI linking.
The EPM9560RC208-7 outputs switch 160 mA DC at 5 ns edge rates, which can generate significant ground bounce on shared ground planes. Place a 22-ohm series damping resistor on each high-fanout output driving more than 4 loads, and route outputs on the top signal layer with a continuous ground plane on layer 2. For 5V PCI bus applications, source-terminate the bus at the EPM9560 output with 33-ohm resistors to match the 65-ohm PCI impedance. JTAG signals (TCK, TMS, TDI, TDO) must be kept short and routed away from switching outputs to prevent programming failures.
Compliance Information
RoHS3 compliant per distributor listing on Alibaba (lead-free terminal finish). The standard EPM9560RC208-7 is Pb-free; the -N suffix variants are explicitly lead-free. AEC-Q100 not applicable as this is a commercial/industrial programmable logic device, not an automotive-qualified IC.
