EPM9560RC208-7 vs EPM9560RC208-10N Comparison

Detailed side-by-side comparison of EPM9560RC208-7 by Altera and EPM9560RC208-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EPM9560RC208-10N EPM9560RC208-10N - MAX 9000 CPLD 560 Macro 10ns 208-RQFP | Intel

EPM9560RC208-10N - MAX 9000 CPLD 560 Macro 10ns 208-RQFP | Intel

EPM9560RC208-10N ⚠ Last Time Buy

Specification Comparison

Parameter EPM9560RC208-7 EPM9560RC208-10N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $18.90 $175.00
Family MAX 9000 MAX 9000
Device Type EPLD / CPLD β€”
Usable Gates 560 12,000
Macrocells 16 β€”
Logic Array Blocks (LABs) 4 16
User I/O Pins 208 153
Pin-to-Pin Delay (tPD) 7 ns (speed grade -7) β€”
Maximum Frequency (fMAX) [DATA_NEEDED: fMAX value] β€”
Supply Voltage (VCCINT) 5.0 V 5.0 V
Supply Voltage (VCCIO) 5.0 V (TTL) or 3.3 V (LVCMOS with level translator) β€”
Process Technology 0.65 um CMOS EEPROM CMOS EEPROM
Configuration Memory Non-volatile on-chip EEPROM (no boot PROM required) β€”
Programming Interface JTAG (IEEE 1149.1) + Altera ISP β€”
Package 208-pin Power Quad Flat Pack (RQFP-208) 208-pin RQFP (Power Quad Flat Pack)
Operating Temperature 0C to +70C (commercial) / -40C to +85C (industrial) [DATA_NEEDED: operating temperature grade]
Output Drive Current 160 mA DC sink per pin β€”
RoHS Status Compliant (ROHS3 per distributor listing) [DATA_NEEDED: RoHS status]
Device β€” EPM9560
Macro Cells β€” 560
Pin-to-Pin Delay (tPD1) β€” 10 ns
I/O Bank Voltage (VCCIO) β€” 5.0 V
Mounting Type β€” Surface Mount
Programmability β€” In-system via IEEE 1149.1 JTAG

Datasheets & Resources

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