EPM9560RC240-12 vs EPM9560RC240-1O Comparison
Detailed side-by-side comparison of EPM9560RC240-12 by Altera and EPM9560RC240-1O by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560RC240-1O - MAX 9000 CPLD, 560 Macrocells, 216 I/O, RQFP-240 | Altera
EPM9560RC240-1O β Last Time BuySpecification Comparison
| Parameter | EPM9560RC240-12 | EPM9560RC240-1O |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $51.07 |
| Family | MAX 9000 (EPM9560) | MAX 9000 |
| Device Type | EE PLD / CPLD | β |
| Macrocells | 560 | 560 |
| Flip-Flops | 772 | β |
| User I/O Pins | 191 | β |
| Logic Array Blocks (LABs) | 20 | 35 |
| Maximum Propagation Delay (tPD) | 13.4 ns | β |
| Speed Grade | -12 (13.4 ns tPD) | β |
| Maximum Operating Frequency (estimated) | ~76 MHz registered | β |
| Core Supply Voltage (VCCINT) | 5 V | β |
| I/O Logic Levels | 3.3 V or 5 V (configurable) | β |
| Package | PQFP-240 (RC240) 0.500 mm pitch, gull-wing | RQFP-240 (240-pin Reduced-height QFP) |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | β |
| Programming Interface | IEEE 1149.1 JTAG | β |
| Process Technology | CMOS | CMOS EEPROM, 0.65 um |
| Operating Temperature | [DATA_NEEDED: operating temperature grade] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | Compliant (per Altera/Intel product page) |
| Usable Gates | β | 12,000 |
| Maximum User I/O Pins | β | 216 |
| Propagation Delay (tPD) | β | 12 ns (typ, -1 speed grade) |
| Global Setup Time (tFSU) | β | 3.0 ns |
| Clock-to-Output (tFCO) | β | 4.8 ns |
| Maximum Internal Frequency (fCNT) | β | 145 MHz |
| Supply Voltage (VCC) | β | 5.0 V |
| Operating Temperature (Grade) | β | -40C to +85C (industrial, "-1O" suffix) |
| Programming | β | In-system programmable via IEEE 1149.1 JTAG |
| Architecture | β | Multiple Array MatriX (MAX), third generation |
| Lead-Free | β | Yes |