EPM9560RC240-1O - MAX 9000 CPLD, 560 Macrocells, 216 I/O, RQFP-240 | Altera
MPN: EPM9560RC240-1O β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $78.5 | $78.50 |
| 10 | $70.65 | $706.50 |
| 100 | $63.21 | $6,321.00 |
| 500 | $56.94 | $28,470.00 |
| 1,000 | $51.07 | $51,070.00 |
EPM9560RC240-1O Overview
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL with the density of small FPGAs, sitting in the broader taxonomy of programmable logic devices (PLD) alongside simple PLDs (SPLD), FPGAs, and structured ASICs. CPLDs are typically used for glue logic, bus interfacing, state machines, and power-up sequencing where instant-on (no boot PROM) and deterministic timing are required. Compared with FPGAs, CPLDs offer lower density but faster, fixed-input-to-output delays that are independent of routing, making the EPM9560RC240-1O well suited to high-fan-in decoder and address-decoding tasks.
Key features include 4.8 ns clock-to-output (tCO) delay, 3.0 ns global setup time, 5V tolerant I/O, and the 240-pin RQFP (Reduced-height Quad Flat Pack) surface-mount package. The MAX 9000 family is fabricated on a 0.65 um CMOS EEPROM process, allowing 100% in-system programmability for rapid prototyping and field upgrades. The EPM9560RC240-1O is the lower-cost industrial-temperature variant of the EPM9560RC240 family, distinguished from the -15, -20 speed grades only by the device timing bin and the operating temperature suffix.
Typical applications for the EPM9560RC240-1O span telecommunications backplane glue logic, industrial control board-level integration, peripheral bus decoding (PCI, VME, ISA), memory-address decoding, DRAM controller interfaces, and high-density state-machine replacement for discrete 7400-series logic. Designers often choose the MAX 9000 family when they need high I/O count, 5V operation, and instant-on behavior without an external configuration memory.
When designing with the EPM9560RC240-1O, ensure the PCB has sufficient thermal copper area for the RQFP-240 package and that signal integrity is preserved on the high-speed 144 MHz I/O paths. Designers should follow Altera's JTAG programming guidelines (ByteBlaster or BitBlaster) and respect the 5V VCCIO tolerance when interfacing to mixed-voltage peripherals. Because the MAX 9000 family is in mature production status, lead times and lifecycle should be confirmed with the supply chain before new design starts.
Drop-in alternatives for EPM9560RC240-1O β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM9560RC240-1O (same form factor and footprint) β differing in Package, Operating Temperature, Configuration Memory, Logic Array Blocks (LABs), Usable Gates.
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EPM9560RC240-15
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$174.72 / Unit
View Datasheet βEPM9560RC240-20
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$122 / Unit
View Datasheet βEPM9560RC240-10
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View Datasheet βEPM9560RC240-12
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$9.95 / Unit
View Datasheet βEPM9560ARC240-10
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$28.8 / Unit
View Datasheet βEPM9560ARI240-10
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View Datasheet βEPM9560RC/ARC240
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$61 / Unit
View Datasheet βEPM9560ARI240-10N
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$105 / Unit
View Datasheet βEPM9560RC240-1O Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Usable Gates | 12,000 |
| Macrocells | 560 |
| Logic Array Blocks (LABs) | 35 |
| Maximum User I/O Pins | 216 |
| Propagation Delay (tPD) | 12 ns (typ, -1 speed grade) |
| Global Setup Time (tFSU) | 3.0 ns |
| Clock-to-Output (tFCO) | 4.8 ns |
| Maximum Internal Frequency (fCNT) | 145 MHz |
| Supply Voltage (VCC) | 5.0 V |
| Operating Temperature (Grade) | -40C to +85C (industrial, "-1O" suffix) |
| Process Technology | CMOS EEPROM, 0.65 um |
| Programming | In-system programmable via IEEE 1149.1 JTAG |
| Architecture | Multiple Array MatriX (MAX), third generation |
| Package | RQFP-240 (240-pin Reduced-height QFP) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (per Altera/Intel product page) |
| Lead-Free | Yes |
EPM9560RC240-1O rqfp-240 (240-pin reduced-height qfp) Pin Configuration Guide
Pin configuration for EPM9560RC240-1O (rqfp-240 (240-pin reduced-height qfp) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RC240-1O.
Refer to the datasheet for full pin configuration.
Typical Applications
EPM9560RC240-1O is suitable for 6 applications: Telecommunications Backplane Glue Logic, Industrial Control Board Integration, PCI/ISA/VME Peripheral Bus Decoding, Memory Address Decoding and DRAM Control, High-Density State Machine Replacement, 5V Avionics and Military Legacy Interfaces.
Telecommunications Backplane Glue Logic
The EPM9560RC240-1O is well-suited to telecom backplane glue-logic boards where 5V-tolerant I/O, 216 user I/O pins, and instant-on non-volatile configuration are essential. Its 12,000 usable gates and 560 macrocells easily absorb wide bus decode, parity generation, and channel-bank steering logic on legacy TDM and SONET backplanes, while the 145 MHz internal frequency handles high-speed serial control paths. The 240-pin RQFP footprint provides the wide I/O fan-out required for 32-bit and 64-bit parallel buses. Designers can integrate what previously required multiple 7400-series TTL packages into one CPLD, reducing board area and improving noise margin.
Recommended
Industrial Control Board Integration
On industrial PLC and process-control boards, the EPM9560RC240-1O replaces dozens of discrete SSI/MSI logic ICs, integrating motor-control state machines, sensor-multiplexer decoding, and safety-interlock logic into one 5V device. Its -40C to +85C industrial temperature rating tolerates factory-floor thermal stress, while the EEPROM configuration survives brown-out and brown-in events with no boot latency. The 216 user I/O pins support direct connection to 24V-tolerant opto-isolated inputs via external resistor dividers. Compared with FPGA solutions, the MAX 9000 deterministic timing ensures motor-step and PWM signals are generated with predictable latency, critical for closed-loop control stability.
Recommended
PCI/ISA/VME Peripheral Bus Decoding
The EPM9560RC240-1O delivers the high fan-in decoder logic required for legacy PCI, ISA, and VME peripheral boards, where multiple chip-select and address-decode signals must be generated with sub-15 ns latency. With 12 ns pin-to-pin tPD and 560 macrocells, the device can implement full address decode for an entire 32-bit peripheral window plus interrupt acknowledge and bus-arbiter glue in a single chip. The 5V I/O directly interfaces with classic PCI/ISA signaling levels without external level shifters. The non-volatile EEPROM ensures bus-decoder logic is active at power-on, before any processor or BIOS initializes, enabling instant peripheral enumeration.
Recommended
Memory Address Decoding and DRAM Control
The EPM9560RC240-1O is well-matched to memory-interface glue such as bank-address decoders, RAS/CAS steering logic, and refresh-state machines for legacy DRAM and SRAM arrays. Its 12 ns tPD comfortably meets the 70 ns row-access timing of standard EDO and page-mode DRAMs used in 1990s-era VME and VXI instrumentation. With 216 I/O pins, the device can simultaneously decode multiple memory banks and generate per-bank chip enables without external buffers. The deterministic MAX architecture guarantees that the address-decode path adds a fixed delay regardless of routing, simplifying timing closure in bus-cycle analysis.
Recommended
High-Density State Machine Replacement
The EPM9560RC240-1O replaces hundreds of 7400-series TTL packages implementing complex multi-state machines, replacing entire schematics with one CPLD plus a JTAG programming header. The 560 macrocells and 35 LABs deliver abundant registered logic for protocols such as I2C master/slave, SPI controller, HDLC framer, or custom motor-control sequencers. The 145 MHz maximum internal frequency supports 50 MHz+ state-clock operation. Designers can iterate the state machine in software (MAX+PLUS II / Quartus) and re-program the EEPROM configuration in-circuit, slashing development cycles compared to discrete TTL breadboards.
Recommended
5V Avionics and Military Legacy Interfaces
The EPM9560RC240-1O's 5V supply tolerance and industrial temperature envelope suit legacy avionics, military, and shipboard electronic systems that still rely on 5V TTL signaling levels and require deterministic, rugged logic. With 12,000 usable gates and 216 I/O pins, the device can implement MIL-STD-1553 bus monitors, ARINC 429 receivers, or weapons-system interface glue on a single chip. The RQFP-240 ceramic-friendly package is compatible with standard MIL-PCB assembly processes. Designers should verify the latest MIL-PRF and RoHS exemption status with the manufacturer for new defense designs.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC240-1O β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC240-15 | EPM9560RC240-20 | EPM9560ARC240-10 | EPM9560RC240-10 |
|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | RQFP-240 | RQFP-240 - same | RQFP-240 - same | RQFP-240 - same | RQFP-240 - same |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Macrocells | 560 | 560 | 560 | 560 | 560 |
| Maximum User I/O | 216 | 216 | 216 | 216 | 216 |
| Pin-to-Pin Delay (tPD) | 12 ns (-1 speed grade) | 10 ns | 11.4 ns | 10 ns (A revision) | 10 ns |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
Key Differentiators
- Industrial temperature grade (-40C to +85C) at the slower -1 speed bin (vs EPM9560RC240-15)
- Larger 560-macrocell density than MAX 7000 series (vs EPM7256SQC208-10)
- Mature 5V-native I/O for legacy backplanes (vs MAX V 5M570ZT100C5N)
- More I/O pins than most same-density CPLDs (vs EPM9560GC280-20)
Design Notes
The RQFP-240 plastic package has a typical theta_JA in the 25-35 C/W range when soldered to a JEDEC test board with 1-oz copper, so at 5V VCC the device dissipation (typically <1.5W worst case for full 145 MHz operation) is within the natural-convection envelope. However, designers should still spread thermal copper under the package and avoid placing the CPLD directly next to high-heat sources such as switching regulators. For sealed industrial enclosures without forced airflow, validate junction temperature by measurement under worst-case ambient.
Use a four-layer PCB with continuous ground and power planes for the RQFP-240 footprint; the 0.5 mm pitch of the package requires 0.25 mm via-in-pad or dog-bone fan-out, 8 mil traces, and 4 mil clearance for reliable fabrication. Place the JTAG header (TCK/TMS/TDO/TDI/TRST) within 6 inches of the CPLD for noise-free in-system programming with ByteBlaster or BitBlaster cables. Decouple each VCC pin pair with 0.1 uF X7R ceramic plus a single 10 uF bulk capacitor near the package center. Assign global clock pins (GCLK1-4) only to the highest-frequency synchronous signals, since each global pin provides matched skew.
Do not confuse the -1O speed/temperature suffix with -10 (commercial, 10 ns tPD) when ordering - the -1O is the slower industrial grade and -10 is a faster commercial grade. Confirm the suffix meaning against the Altera MAX 9000 ordering information before placing volume orders. Also verify that the JTAG chain IDCODE is recognized by MAX+PLUS II / Quartus before soldering, because counterfeit MAX 9000 parts have appeared in the obsolete-market supply chain and may fail IDCODE verification. Finally, do not assume the EPM9560RC240-1O can be substituted for a MAX II or MAX V CPLD - those use different footprints and 3.3V cores, requiring PCB rework.
Although the 12 ns tPD and 145 MHz internal frequency are modest by modern standards, the 216 simultaneous-switching I/O pins can produce significant ground bounce on the RQFP-240 package. Use Altera's recommended pin assignment to spread SSO (simultaneous-switching output) pins across multiple LAB banks, and add 22-33 ohm series damping resistors on heavily-loaded outputs (e.g., memory data buses). For PCI-style buses, follow the AC switching characteristics in the datasheet and add clock-line termination only if reflections are observed on the actual board.
Compliance Information
RoHS compliant per Altera/Intel product environmental documentation. Not AEC-Q100 qualified (automotive grade) - MAX 9000 family is targeted at industrial and legacy commercial designs. Lead-free and halogen-free finish standard on the RC package suffix. Customers should request a current material declaration from the distributor for high-volume production.
