EPM9560RC240-1O vs EPM9560ARI240-10 Comparison
Detailed side-by-side comparison of EPM9560RC240-1O by Intel and EPM9560ARI240-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560RC240-1O - MAX 9000 CPLD, 560 Macrocells, 216 I/O, RQFP-240 | Altera
EPM9560RC240-1O β Last Time BuySpecification Comparison
| Parameter | EPM9560RC240-1O | EPM9560ARI240-10 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $51.07 | $0.00 |
| Family | MAX 9000 | MAX 9000 |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | β |
| Logic Array Blocks (LABs) | 35 | β |
| Maximum User I/O Pins | 216 | β |
| Propagation Delay (tPD) | 12 ns (typ, -1 speed grade) | β |
| Global Setup Time (tFSU) | 3.0 ns | β |
| Clock-to-Output (tFCO) | 4.8 ns | β |
| Maximum Internal Frequency (fCNT) | 145 MHz | β |
| Supply Voltage (VCC) | 5.0 V | β |
| Operating Temperature (Grade) | -40C to +85C (industrial, "-1O" suffix) | β |
| Process Technology | CMOS EEPROM, 0.65 um | β |
| Programming | In-system programmable via IEEE 1149.1 JTAG | β |
| Architecture | Multiple Array MatriX (MAX), third generation | β |
| Package | RQFP-240 (240-pin Reduced-height QFP) | 240-pin RQFP (PowerQuad Flat Pack) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Compliant (per Altera/Intel product page) | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes | β |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macro Cells | β | 560 |
| User I/O Pins | β | 191 |
| Pin-to-Pin Propagation Delay | β | 10 ns |
| Internal Frequency | β | 144.9 MHz |
| Supply Voltage | β | 5.0 V |
| Technology | β | CMOS, EEPROM-based configuration |
| Operating Temperature Range | β | -40 C to +85 C (industrial) |
| Configuration Memory | β | EEPROM (non-volatile, instant-on) |
| Logic Architecture | β | Multiple Array MatriX (MAX) with global interconnect array |
| Moisture Sensitivity Level | β | [DATA_NEEDED: MSL level] |
| Number of Terminals | β | 240 |
| Terminal Form | β | Gull Wing |