EPM9560RI208-15N vs EPM9560RI205-15 Comparison
Detailed side-by-side comparison of EPM9560RI208-15N by Altera and EPM9560RI205-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560RI208-15N
EPM9560RI208-15N - MAX 9000 EPLD, 208-Pin RQFP, 15ns | Altera
EPM9560RI208-15N ObsoleteAltera
EPM9560RI205-15
EPM9560RI205-15 - MAX 9000 CPLD, 6K Gates, 15ns | Altera
EPM9560RI205-15 ObsoleteSpecification Comparison
| Parameter | EPM9560RI208-15N | EPM9560RI205-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $19.45 | $54.00 |
| Manufacturer | Altera (Intel Programmable Solutions Group) | β |
| Device Family | MAX 9000 | β |
| Device Type | EPLD (Erasable Programmable Logic Device) | β |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | β |
| Configuration Memory | CMOS EEPROM, in-system programmable | β |
| Package | 208-pin RQFP (Ruggedized Quad Flat Pack) | RQFP-205 (PowerQuad4) |
| Total Pins | 356 (per third-party catalog; see _validation_note) | β |
| Package Pin Count | 208 | β |
| Terminal Form | Gull Wing | β |
| Package Code | HFQFP | β |
| User I/Os | 216 (per DigiChip specification; see _validation_note) | β |
| Maximum Internal Frequency | 145 MHz | β |
| Propagation Delay (tPD) | 11.4 ns (15 ns speed grade) | β |
| Speed Grade | -15 | -15 (15 ns pin-to-pin delay) |
| Supply Voltage | 5.0 V | β |
| Operating Temperature | 0C to 70C (Commercial) | -40 C to +85 C (industrial) |
| Temperature Grade | Industrial (per Vyrian/Partstack listings) | β |
| Logic Family | CMOS | β |
| Programming Interface | IEEE 1149.1 JTAG, 5.0-V in-system | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs_compliance] |
| Family | β | MAX 9000 |
| Device | β | EPM9560 |
| Logic Capacity | β | 6,000 usable gates |
| Macrocells | β | 212 |
| Logic Array Blocks (LABs) | β | 20 |
| Maximum User I/O Pins | β | 164 |
| Propagation Delay (tpd) | β | 15 ns |
| Supply Voltage (VCC) | β | 5.0 V |
| Technology | β | CMOS EEPROM |
| In-System Programmability | β | Yes (IEEE 1149.1 JTAG) |
| Mounting Type | β | Surface Mount |