EPM9560RI208-15N vs EPM9560RI208-10N Comparison
Detailed side-by-side comparison of EPM9560RI208-15N by Altera and EPM9560RI208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560RI208-15N
EPM9560RI208-15N - MAX 9000 EPLD, 208-Pin RQFP, 15ns | Altera
EPM9560RI208-15N ObsoleteAltera
EPM9560RI208-10N
EPM9560RI208-10N - MAX 9000 CPLD, 12K Gates, 208-Pin RQFP
EPM9560RI208-10N ObsoleteSpecification Comparison
| Parameter | EPM9560RI208-15N | EPM9560RI208-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $19.45 | $61.75 |
| Manufacturer | Altera (Intel Programmable Solutions Group) | β |
| Device Family | MAX 9000 | β |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Configuration Memory | CMOS EEPROM, in-system programmable | On-chip EEPROM (non-volatile) |
| Package | 208-pin RQFP (Ruggedized Quad Flat Pack) | 208-pin RQFP (PQFP) |
| Total Pins | 356 (per third-party catalog; see _validation_note) | β |
| Package Pin Count | 208 | β |
| Terminal Form | Gull Wing | β |
| Package Code | HFQFP | β |
| User I/Os | 216 (per DigiChip specification; see _validation_note) | 212 |
| Maximum Internal Frequency | 145 MHz | β |
| Propagation Delay (tPD) | 11.4 ns (15 ns speed grade) | β |
| Speed Grade | -15 | β |
| Supply Voltage | 5.0 V | 5 V |
| Operating Temperature | 0C to 70C (Commercial) | -40C to +85C (Industrial grade, "RI" suffix) |
| Temperature Grade | Industrial (per Vyrian/Partstack listings) | β |
| Logic Family | CMOS | β |
| Programming Interface | IEEE 1149.1 JTAG, 5.0-V in-system | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | ROHS3 Compliant (per fpgalink) |
| Family | β | MAX 9000 |
| Usable Gates | β | 12,000 |
| Macro Cells | β | 560 |
| Register Bits | β | 12,160 |
| Pin-to-Pin Delay | β | 10 ns (speed grade -10) |
| Maximum Frequency | β | 100 MHz to 125 MHz |
| Programming Method | β | In-system via IEEE 1149.1 (JTAG) |
| MSL Level | β | 3 (168 Hours) |