EPM9560RI208-15N vs EPM9560RI208-20W Comparison
Detailed side-by-side comparison of EPM9560RI208-15N by Altera and EPM9560RI208-20W by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560RI208-15N
EPM9560RI208-15N - MAX 9000 EPLD, 208-Pin RQFP, 15ns | Altera
EPM9560RI208-15N ObsoleteIntel
EPM9560RI208-20W
EPM9560RI208-20W - MAX 9000 CPLD, 12K Gates, 208-Pin | Intel
EPM9560RI208-20W NrndSpecification Comparison
| Parameter | EPM9560RI208-15N | EPM9560RI208-20W |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $19.45 | $48.75 |
| Manufacturer | Altera (Intel Programmable Solutions Group) | β |
| Device Family | MAX 9000 | β |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | Third-generation Multiple Array MatriX (MAX) |
| Configuration Memory | CMOS EEPROM, in-system programmable | β |
| Package | 208-pin RQFP (Ruggedized Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Total Pins | 356 (per third-party catalog; see _validation_note) | β |
| Package Pin Count | 208 | β |
| Terminal Form | Gull Wing | β |
| Package Code | HFQFP | β |
| User I/Os | 216 (per DigiChip specification; see _validation_note) | β |
| Maximum Internal Frequency | 145 MHz | β |
| Propagation Delay (tPD) | 11.4 ns (15 ns speed grade) | β |
| Speed Grade | -15 | -20 |
| Supply Voltage | 5.0 V | 5.0 V |
| Operating Temperature | 0C to 70C (Commercial) | -40C to +85C (Industrial) |
| Temperature Grade | Industrial (per Vyrian/Partstack listings) | β |
| Logic Family | CMOS | β |
| Programming Interface | IEEE 1149.1 JTAG, 5.0-V in-system | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Family | β | MAX 9000 |
| Usable Gates | β | 12,000 |
| Macrocells | β | 560 |
| Logic Array Blocks (LABs) | β | 16 LABs of 40 macrocells each |
| User I/O Pins | β | 212 |
| Pin-to-Pin Delay (tPD) | β | 20 ns |
| Counter Frequency (fCNT) | β | 100 MHz |
| In-System Programmability | β | Yes (IEEE 1149.1 JTAG) |
| Programming Technology | β | CMOS EEPROM |