EPM9560RI208-20N vs EPM9560RI208-15N Comparison
Detailed side-by-side comparison of EPM9560RI208-20N by Intel and EPM9560RI208-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560RI208-20N
EPM9560RI208-20N - MAX 9000 CPLD 12K Gates 208-RQFP | Intel
EPM9560RI208-20N ObsoleteAltera
EPM9560RI208-15N
EPM9560RI208-15N - MAX 9000 EPLD, 208-Pin RQFP, 15ns | Altera
EPM9560RI208-15N ObsoleteSpecification Comparison
| Parameter | EPM9560RI208-20N | EPM9560RI208-15N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $19.45 |
| Device Family | MAX 9000 | MAX 9000 |
| Usable Gates | 12,000 | β |
| Macrocells | 560 | β |
| Pin-to-Pin Delay | 20 ns (-20 speed grade) | β |
| Counter Speed | 100 MHz | β |
| Supply Voltage | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | β |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | β |
| Package | 208-pin RQFP | 208-pin RQFP (Ruggedized Quad Flat Pack) |
| Mounting Type | Surface Mount | β |
| Operating Temperature | Industrial (-40C to +85C) | 0C to 70C (Commercial) |
| Development Tool | MAX+PLUS II | β |
| Design Entry | Schematic, VHDL, Verilog HDL, AHDL | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Packaging | Tray | β |
| Logic Architecture | Third-generation MAX (Multiple Array MatriX) | β |
| Fabrication Process | Advanced CMOS | β |
| Manufacturer | β | Altera (Intel Programmable Solutions Group) |
| Device Type | β | EPLD (Erasable Programmable Logic Device) |
| Architecture | β | Multiple Array MatriX (MAX), 3rd generation |
| Configuration Memory | β | CMOS EEPROM, in-system programmable |
| Total Pins | β | 356 (per third-party catalog; see _validation_note) |
| Package Pin Count | β | 208 |
| Terminal Form | β | Gull Wing |
| Package Code | β | HFQFP |
| User I/Os | β | 216 (per DigiChip specification; see _validation_note) |
| Maximum Internal Frequency | β | 145 MHz |
| Propagation Delay (tPD) | β | 11.4 ns (15 ns speed grade) |
| Speed Grade | β | -15 |
| Temperature Grade | β | Industrial (per Vyrian/Partstack listings) |
| Logic Family | β | CMOS |
| Programming Interface | β | IEEE 1149.1 JTAG, 5.0-V in-system |