EPM9560SRC240-15 vs EPM9560RI240-15 Comparison
Detailed side-by-side comparison of EPM9560SRC240-15 by Altera and EPM9560RI240-15 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560SRC240-15
EPM9560SRC240-15 - MAX 9000 CPLD, 560 Gates, 240-Pin | Intel / Altera
EPM9560SRC240-15 NrndIntel
EPM9560RI240-15
EPM9560RI240-15 - 560-Macrocell MAX 9000 CPLD, 15ns, RQFP-240 | Intel
EPM9560RI240-15 ObsoleteSpecification Comparison
| Parameter | EPM9560SRC240-15 | EPM9560RI240-15 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $22.50 | $23.10 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD / CPLD (Complex Programmable Logic Device) | β |
| Usable Gates | 560 | β |
| Logic Array Blocks (LABs) | 16 | β |
| Macrocells | 212 | 560 |
| Maximum User I/O Pins | [DATA_NEEDED: exact I/O count for SRC240 package] | β |
| Speed Grade | -15 (15 ns tPD) | β |
| Pin-to-Pin Logic Delay (tPD) | 15 ns (max) | β |
| Supply Voltage (VCC) | 5 V (nominal) | β |
| Programmability | In-system programmable via IEEE 1149.1 JTAG | β |
| Non-volatile | Yes (EPROM/EEPROM cells) | β |
| Package | RQFP-240 (Surface Mount) | RQFP-240 (Power Quad Flat Pack, gull-wing, 0.500 mm pitch) |
| Operating Temperature | [DATA_NEEDED: commercial 0-70C or industrial -40-85C] | -40 C to +85 C (industrial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance not stated in provided data] | β |
| Process Technology | CMOS EPROM | β |
| Product Type | β | EE PLD (Electrically Erasable Programmable Logic Device) |
| Flip-Flops | β | 772 |
| User I/Os (industrial grade) | β | 191 |
| Dedicated Inputs | β | 4 |
| Propagation Delay (tPD) | β | 15 ns (speed grade -15) |
| Internal Frequency (max) | β | 145 MHz |
| Logic Family / Process | β | CMOS, EEPROM-based |
| Core Voltage | β | 5.0 V |
| I/O Voltage | β | 3.3 V or 5.0 V (configurable) |
| Architecture | β | Multiple Array MatriX (MAX), 3rd generation |
| In-System Programmability | β | Yes, JTAG (IEEE Std 1149.1) |
| Power-Up Configuration | β | Instant-on (no external boot PROM) |
| I/O Undershoot Tolerance | β | -2.0 V for <20 ns (no-load) |
| I/O Overshoot Tolerance | β | 7.0 V for <20 ns (no-load) |