EPM9560WC208-15 vs EPM9560RC208-15C Comparison

Detailed side-by-side comparison of EPM9560WC208-15 by Altera and EPM9560RC208-15C by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM9560WC208-15

EPM9560WC208-15 - 560-Macrocell EE PLD, 117.6 MHz | Altera

EPM9560WC208-15 Obsolete
Altera
EPM9560RC208-15C

EPM9560RC208-15C - MAX 9000 CPLD 560 Macro Cells | Altera

EPM9560RC208-15C Obsolete

Specification Comparison

Parameter EPM9560WC208-15 EPM9560RC208-15C
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $105.00 $0.00
Family MAX 9000 MAX 9000
Device Type EE PLD (Electrically Erasable Programmable Logic Device) EEPROM-based CPLD (EPLD)
Technology CMOS β€”
Macrocells 560 560
Logic Array Blocks (LABs) 35 β€”
Flip-Flops 772 β€”
User I/O Pins (max) 149 β€”
Maximum Clock Frequency 117.6 MHz β€”
Propagation Delay (tPD) 16.6 ns 15 ns
Speed Grade -15 -15 (15 ns)
Supply Voltage - I/O 3.3 V or 5.0 V (configurable) β€”
Package 208-pin CQFP (Ceramic Quad Flat Pack) 208-pin RQFP
Terminal Pitch 0.50 mm β€”
Mounting Type Surface Mount Surface Mount
Programming Interface JTAG (IEEE 1149.1 boundary scan) β€”
RoHS Status RoHS3 Compliant (per third-party listings) [DATA_NEEDED: RoHS status]
Usable Gates β€” 12,000
User I/O Pins β€” 149
Maximum Counter Frequency β€” 117.6 MHz
Supply Voltage Range β€” 4.75 V to 5.25 V
Nominal Supply Voltage β€” 5.0 V
I/O Voltage Compatibility β€” 3.3 V or 5 V
Configuration Memory β€” EEPROM (non-volatile)
In-System Programmability β€” Yes, via IEEE Std. 1149.1 JTAG
Operating Temperature Range β€” 0C to +70C (commercial)
Logic Architecture β€” Multiple Array MatriX (MAX) third generation

Datasheets & Resources

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