EPM9560WC208-20 vs EPM9560RC208-20N Comparison
Detailed side-by-side comparison of EPM9560WC208-20 by Altera and EPM9560RC208-20N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560WC208-20
EPM9560WC208-20 - 560-Macrocell CPLD, 23.6ns, PQFP-208 | Intel/Altera
EPM9560WC208-20 ObsoleteIntel
EPM9560RC208-20N
EPM9560RC208-20N - MAX 9000 CPLD 560 Macrocell 20ns | Intel
EPM9560RC208-20N ObsoleteSpecification Comparison
| Parameter | EPM9560WC208-20 | EPM9560RC208-20N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $25.80 | $0.00 |
| Family | MAX 9000 | β |
| Device Type | CPLD (EPLD) | β |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | β |
| User I/O Pins | 149 | 149 |
| Maximum Propagation Delay (tPD) | 23.6 ns | β |
| Package | PQFP-208 (RQFP/WQFP) | 208-pin RQFP (PowerQuad Flat Pack) |
| Process Technology | CMOS, EEPROM-based | β |
| Supply Voltage (VCCINT) | 5 V (typical, see datasheet) | β |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (multi-voltage I/O) | β |
| In-System Programmability | Yes, JTAG BST (IEEE 1149.1) | Yes, via IEEE Std. 1149.1 JTAG |
| Pin/Package Suffix | W = power PQFP; -20 = 23.6 ns speed grade | β |
| Operating Temperature | Commercial (0C to +70C) [DATA_NEEDED: exact temp grade] | [DATA_NEEDED: operating temperature range] |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Non-compliant (legacy PQFP) [DATA_NEEDED: confirm from official doc] | Lead-free (N suffix) |
| Lead-Free | [DATA_NEEDED] | β |
| Halogen-Free | [DATA_NEEDED] | β |
| MSL Level | [DATA_NEEDED] | [DATA_NEEDED: MSL level] |
| Device Family | β | MAX 9000 (EPM9560) |
| Usable Gates | β | 12,000 |
| Propagation Delay (tPD) | β | 20 ns |
| Supply Voltage | β | 5.0 V |
| Configuration Technology | β | EEPROM (non-volatile) |
| JTAG Interface | β | IEEE Std. 1149.1 |
| Logic Architecture | β | Multiple Array MatriX (MAX), third-generation CMOS EEPROM |
| Flip-Flops | β | 772 (per EPM9560 series data) |
| Speed Grade | β | -20 (20 ns) |