RTAX250S-CQ352V - 250K-Gate Rad-Tolerant FPGA CQFP-352 | Microchip
MPN: RTAX250S-CQ352V ✓ Active| Qty | Unit Price | Extended |
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Drop-in alternatives for RTAX250S-CQ352V — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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RTAX250S-1CQ352V
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$1395 / Unit
View Datasheet →RTAX250SL-CQ352V
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View Datasheet →RTAX250SL-1CQ352V
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View Datasheet →RTAX1000SL-CQ352V
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View Datasheet →RTAX250S-CQ352V Maximum Ratings & Electrical Characteristics
| Family | RTAX-S (Radiation-Tolerant FPGA) |
| Equivalent System Gates | 250000 gates |
| Logic Cells | 4224 |
| CLBs | 2816 |
| Process Technology | 0.15 um CMOS |
| Core Supply Voltage | 1.5 V nominal (1.425 V to 1.575 V) |
| Maximum Frequency | 649 MHz |
| Package | 352-Pin CQFP (Ceramic Quad Flat Pack) |
| Mounting Type | Surface Mount |
| Programming Technology | Antifuse (one-time programmable) |
| Speed Grade | Standard (blank suffix) |
| Radiation Tolerance | Radiation-tolerant (space-flight qualified) |
| Configuration | Single-chip, live at power-up |
RTAX250S-CQ352V 352-pin cqfp (ceramic quad flat pack) Pin Configuration Guide
Complete pinout information for RTAX250S-CQ352V (352-pin cqfp (ceramic quad flat pack) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for RTAX250S-CQ352V.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
RTAX250S-CQ352V is suitable for 6 applications: Satellite Avionics and Platform Control, Payload Data Processing, Telemetry and Telecommand Interfaces, Instrument Control and Sequencing, Space Flight Reprogrammable Prototyping Flow, Deep-Space and High-Radiation Missions.
Satellite Avionics and Platform Control
The RTAX250S-CQ352V fits spacecraft avionics because it combines 250,000 usable system gates with live-at-power-up antifuse configuration, eliminating the boot failure modes associated with SRAM FPGAs and external configuration memories. In a platform computer, it typically implements the housekeeping state machine, mode transitions, redundant two-out-of-three voting logic, and MIL-STD-style serial telecommand/telemetry interfaces at modest clock rates well within its 649 MHz fabric capability. The hermetic 352-pin CQFP withstands launch vibration and thermal vacuum cycling better than plastic packaging. Because it draws low static power on a 1.5 V nominal core (1.425 V to 1.575 V), it suits solar- and battery-powered buses with tight power budgets. Designers verify the logic in the Axcelerator prototyping flow (application note AC170) before programming the OTP flight unit.
Recommended
Payload Data Processing
For imaging, spectroscopy, and scientific payloads, the RTAX250S-CQ352V provides glueless framing, buffering, and front-end formatting logic between sensors and downlink chains. Its 4,224 logic cells (2,816 CLBs) absorb functions such as CRC generation, packetization, and interface bridging, while the standard speed grade covers the tens-of-MHz to low-hundreds-of-MHz clock domains typical of payload processing. Because the antifuse fabric configuration is immune to single-event configuration upsets, only user registers need SEU mitigation such as triple-module redundancy, simplifying the reliability analysis. The 1.5 V core supply (1.425 V to 1.575 V) supports low-power continuous operation in orbit. The CQFP-352 hermetic ceramic package with surface mounting provides the trackability and screening heritage required by space payload integrators for flight-lot acceptance.
Recommended
Telemetry and Telecommand Interfaces
The RTAX250S-CQ352V is well matched to TM/TC subsystems because these functions demand modest logic capacity but very high configuration reliability. The device implements telemetry formatters, command decoders, and time-tagging counters at the protocol clock rates involved, comfortably within the 649 MHz fabric ceiling. Live-at-power-up behavior matters here: telemetry and safety channels are available immediately when the spacecraft powers on, without any configuration load time or boot sequencing, a property Microchip explicitly cites for the RTAX-S family. The 352-pin CQFP offers enough I/O to bond out redundant command cross-straps, multiple serial interfaces, and dedicated test pins required by failure-tolerant TM/TC architectures. Designers typically pair the FPGA with rad-tolerant power and supervisor components on the same flight board.
Recommended
Instrument Control and Sequencing
Science instruments on LEO and deep-space missions use the RTAX250S-CQ352V as the sequencing and control controller: driving detector clocks, coordinating analog-front-end sampling, and enforcing interlock logic. The antifuse, one-time-programmable nature of the fabric means once sequencer logic is verified it cannot be corrupted in flight, which is critical for instruments with high-voltage or cryogenic subsystems where erroneous clocks cause damage. The 1.5 V nominal supply with 1.425 V to 1.575 V tolerance simplifies clean power-tree design for noise-sensitive analog sections. Its 250K-gate capacity is sufficient for most instrument sequencers, while the CQFP-352 package provides the hermeticity and pin count for redundant control lines. Sequencer designs are prototyped on commercial Axcelerator parts per Microchip AC170 before flight programming.
Recommended
Space Flight Reprogrammable Prototyping Flow
Although the RTAX250S-CQ352V itself is OTP, it anchors a documented prototyping ecosystem. Microchip application note AC170 and the RTAX-S/SL datasheet describe a flow that targets the RTAX-S design to the equivalent commercial Axcelerator device, using Extender circuit boards that map the commercial package footprint to the RTAX-S CQ352 package. Aldec, in partnership with Microchip, additionally offers flash-based ProASIC3E adaptor solutions (such as the ACT-H3Ki-CQ352, footprint-compatible with CQ352 RTAX parts) enabling iterative, reprogrammable verification. Teams therefore develop, simulate, and iterate on reprogrammable silicon, then commit the verified netlist once to the RTAX250S-CQ352V flight device, minimizing the risk inherent in one-time programming of expensive space-grade parts.
Recommended
Deep-Space and High-Radiation Missions
For missions beyond low-Earth orbit, where TID accumulation and single-event fluxes are severe, the RTAX250S-CQ352V offers an architecture-level advantage: permanent antifuse interconnect cannot suffer configuration memory upsets, the dominant failure mechanism of SRAM FPGAs in deep space. Microchip markets RTAX-S as the FPGA of choice for space-flight systems, citing low power, single-chip form factor, and live-at-power-up operation. The 250K-gate density suits autonomy logic, fault-management computers, and interface bridges in cruise-stage and probe electronics. The 0.15 um CMOS process and 1.5 V core operation keep dynamic power low over multi-year missions. Program offices should obtain the family TID and SEE test data package from Microchip space products to close radiation design margins for the specific trajectory.
Recommended
Recommended Products Summary
Engineering reference data for RTAX250S-CQ352V — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | RTAX250S-1CQ352V | RTAX250SL-CQ352V | RTAX250SL-1CQ352V | RTAX1000SL-CQ352V |
|---|---|---|---|---|---|
| Package | CQFP-352 | CQFP-352 - same | CQFP-352 - same | CQFP-352 - same | CQFP-352 - same |
| Brand | Microchip Technology (Actel/Microsemi) | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Equivalent System Gates | 250000 | 250000 | 250000 | 250000 | 1000000 |
| Speed Grade | Standard (blank) | 1 (~15% faster) | Standard (blank) | 1 (~15% faster) | Standard (blank) |
| Family / Process | RTAX-S, 0.15 um CMOS | RTAX-S, 0.15 um CMOS | RTAX-SL, 0.15 um CMOS | RTAX-SL, 0.15 um CMOS | RTAX-SL, 0.15 um CMOS |
| Core Supply Voltage | 1.5 V (1.425 V - 1.575 V) | 1.5 V (1.425 V - 1.575 V) | 1.5 V (1.425 V - 1.575 V) | 1.5 V (1.425 V - 1.575 V) | 1.5 V (1.425 V - 1.575 V) |
| Radiation Tolerance | Radiation-tolerant (RTAX-S) | Radiation-tolerant | Radiation-tolerant (SL) | Radiation-tolerant (SL) | Radiation-tolerant (SL) |
| Availability on XAIPART | Product page available | Product page available | Product page available | Product page available | Product page available |
Key Differentiators
- Identical die, faster timing without board change (vs RTAX250S-1CQ352V)
- SL low-power process option on same footprint (vs RTAX250SL-CQ352V)
- Fourfold capacity headroom without PCB respin (vs RTAX1000SL-CQ352V)
Design Notes
The RTAX250S-CQ352V is one-time programmable (OTP antifuse). Never program a flight unit without completing full functional verification, timing closure, and simulation sign-off. Microchip application note AC170 documents the recommended flow: target the design to the equivalent commercial Axcelerator device (e.g., AX250) with Extender boards mapping the commercial package to the RTAX-S CQ352 footprint, or use the non-hermetic RTAX250S-1CQ352PROTO device that carries the same functional characteristics as the flight unit. Budget schedule time for this verification cycle; OTP errors require a new flight part.
Design the core rail for 1.5 V nominal with 1.425 V to 1.575 V tolerance per the RTAX-S datasheet. Actual current depends on the placed design, so run Microchip Libero power estimation on the final netlist rather than assuming worst-case die current - this avoids over-sizing the space-qualified point-of-load converter. Add bulk and 0.1 uF decoupling at each CQFP power pin pair with short, wide traces, and verify rail sequencing and inrush behavior of upstream rad-tolerant regulators under cold-start at minimum input voltage.
The 352-pin CQFP has relatively long, inductive leads compared to area-array packages; keep I/O edge rates and trace stubs controlled for interfaces above roughly 100 MHz, and series-terminate lines routed to off-board loads. Assign JTAG and dedicated configuration/programming pins early in schematic capture so boundary-scan access is preserved on the assembled board. Follow Microchip RTAX-S design and layout guidance for I/O bank assignment, and account for the hermetic ceramic package's mechanical bonding requirements (lead-forming and solder profile) during board assembly planning.
Compliance Information
Space-grade hermetic ceramic-packaged FPGA; compliance declarations for RoHS/REACH/lead content are not stated in the provided web data and must be requested from Microchip space products documentation.
