SN74LS138 - 3-to-8 Line Decoder/Demultiplexer | Texas Instruments
MPN: SN74LS138 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0.45 | $0.45 |
| 10 | $0.38 | $3.80 |
| 100 | $0.29 | $29.00 |
| 500 | $0.24 | $120.00 |
| 1,000 | $0.19 | $190.00 |
Drop-in alternatives for SN74LS138 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
SN74LS138N
β Drop-Inπ Reference alternative (not in catalog)
SN74LS138D
β Drop-Inπ Reference alternative (not in catalog)
SN74LS138NS
β Drop-Inπ Reference alternative (not in catalog)
MC74LS138
β Drop-Inπ Reference alternative (not in catalog)
74HC138
β Drop-Inπ Reference alternative (not in catalog)
74HCT138
β Drop-Inπ Reference alternative (not in catalog)
SN74LS138 Maximum Ratings & Electrical Characteristics
| Function | 3-to-8 line decoder/demultiplexer |
| Number of Inputs | 3 (A, B, C) |
| Number of Outputs | 8 (Y0-Y7, active-low) |
| Enable Inputs | 3 (G1 active-high, G2A and G2B active-low) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V |
| Propagation Delay Time (tpd) | 20 ns (typical) |
| Output Current (IOL) | 8 mA (sink) |
| Power Dissipation | 32 mW (typical) |
| Operating Temperature Range | 0Β°C to 70Β°C |
| Technology | Schottky-clamped TTL (LS) |
| Package Type | 16-PDIP (N), 16-SOIC (D), 16-SOP (NS) |
| Mounting Type | Through-hole (PDIP) or Surface Mount (SOIC/SOP) |
| Logic Family | 74LS |
| RoHS Status | Compliant |
| MSL Level | 1 (unlimited) |
SN74LS138 Pin Configuration
| Pin 1 | A β Select input A (LSB) |
| Pin 2 | B β Select input B |
| Pin 3 | C β Select input C (MSB) |
| Pin 4 | G2A β Enable input (active-low) |
| Pin 5 | G2B β Enable input (active-low) |
| Pin 6 | G1 β Enable input (active-high) |
| Pin 7 | Y7 β Output 7 (active-low) |
| Pin 8 | GND β Ground |
| Pin 9 | Y6 β Output 6 (active-low) |
| Pin 10 | Y5 β Output 5 (active-low) |
| Pin 11 | Y4 β Output 4 (active-low) |
| Pin 12 | Y3 β Output 3 (active-low) |
| Pin 13 | Y2 β Output 2 (active-low) |
| Pin 14 | Y1 β Output 1 (active-low) |
| Pin 15 | Y0 β Output 0 (active-low) |
| Pin 16 | VCC β Positive supply voltage (5V) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
SN74LS138 is suitable for 6 applications: Memory Chip Select Decoding, Data Routing and Demultiplexing, Address Decoding in Peripheral Interfaces, Industrial Control Logic, Educational and Prototyping, Test and Measurement Equipment.
Memory Chip Select Decoding
The SN74LS138 is ideal for memory chip select address decoding in microprocessor systems. Its three enable inputs allow cascading to create larger decoders, and its active-low outputs directly drive active-low chip select pins on memory devices. The short propagation delay (20 ns) ensures fast access times, making it suitable for high-speed bipolar memory decoding. For example, in an 8085-based system, the SN74LS138 can decode the upper address lines to select among multiple memory banks, ensuring each chip is enabled only when its address range is accessed.
Recommended
Data Routing and Demultiplexing
The SN74LS138 can be used as a demultiplexer to route a single data line to one of eight outputs based on the select inputs. This is useful in data acquisition systems where multiple sensors share a single data bus. The active-low outputs allow direct connection to tri-state buffers or latches. With a propagation delay of 20 ns, it can handle high-speed data routing in multiplexed systems. For example, in a telemetry system, the SN74LS138 can select which sensor's data is placed on the bus, enabling efficient data collection from multiple channels.
Recommended
Address Decoding in Peripheral Interfaces
In peripheral interface circuits, the SN74LS138 decodes address lines to select specific I/O devices. Its three enable inputs provide flexibility for enabling the decoder only when the CPU is accessing the I/O space. The active-low outputs can directly drive chip select pins on peripheral ICs such as UARTs, timers, and parallel ports. The 20 ns propagation delay ensures minimal address-to-chip-select delay, improving system performance. For example, in a Z80-based system, the SN74LS138 can decode the I/O address lines to select among multiple peripheral devices, ensuring each device responds only to its assigned address.
Recommended
Industrial Control Logic
The SN74LS138 is used in industrial control systems for selecting among multiple actuators or sensors based on a binary control word. Its TTL compatibility allows direct interfacing with PLCs and other industrial logic. The active-low outputs can drive relays or optocouplers through appropriate drivers. The wide operating temperature range (0Β°C to 70Β°C) makes it suitable for most industrial environments. For example, in a conveyor belt control system, the SN74LS138 can decode a 3-bit sensor address to activate the corresponding motor driver, enabling efficient routing of items to different destinations.
Recommended
Educational and Prototyping
The SN74LS138 is a staple in digital electronics education and prototyping. Its simple 3-to-8 decoding function makes it ideal for teaching combinational logic design. The PDIP package is breadboard-friendly, allowing students to build and test circuits quickly. The device's robustness and wide availability make it a reliable choice for classroom experiments. For example, in a digital logic lab, students can use the SN74LS138 to implement a 3-bit binary to octal display, demonstrating the principles of decoding and demultiplexing.
Recommended
Test and Measurement Equipment
In test and measurement equipment, the SN74LS138 is used for channel selection in multi-channel data acquisition systems. Its fast propagation delay (20 ns) ensures accurate timing in high-speed sampling applications. The active-low outputs can enable analog multiplexers or sample-and-hold circuits. The device's TTL compatibility allows easy integration with other logic families. For example, in a logic analyzer, the SN74LS138 can decode the channel address to select which input is routed to the acquisition memory, enabling simultaneous monitoring of multiple digital signals.
Recommended
Recommended Products Summary
Engineering reference data for SN74LS138 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SN74LS138N | SN74LS138D | SN74LS138NS | MC74LS138 | 74HC138 | 74HCT138 |
|---|---|---|---|---|---|---|---|
| Package | 16-PDIP | 16-PDIP | 16-SOIC | 16-SOP | 16-PDIP | 16-PDIP | 16-PDIP |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | onsemi | NXP Semiconductors | NXP Semiconductors |
| Technology | Schottky TTL (LS) | Schottky TTL (LS) | Schottky TTL (LS) | Schottky TTL (LS) | Schottky TTL (LS) | High-speed CMOS | High-speed CMOS (TTL compatible) |
| Propagation Delay (typical) | 20 ns | 20 ns | 20 ns | 20 ns | 20 ns | 20 ns (at 5V) | 20 ns (at 5V) |
| Output Sink Current (IOL) | 8 mA | 8 mA | 8 mA | 8 mA | 8 mA | 4 mA | 4 mA |
| Supply Voltage Range | 4.75V to 5.25V | 4.75V to 5.25V | 4.75V to 5.25V | 4.75V to 5.25V | 4.75V to 5.25V | 2V to 6V | 4.5V to 5.5V |
| Power Dissipation (typical) | 32 mW | 32 mW | 32 mW | 32 mW | 32 mW | 0.5 mW (at 5V, no load) | 0.5 mW (at 5V, no load) |
| Operating Temperature Range | 0Β°C to 70Β°C | 0Β°C to 70Β°C | 0Β°C to 70Β°C | 0Β°C to 70Β°C | 0Β°C to 70Β°C | -40Β°C to 85Β°C | -40Β°C to 85Β°C |
Key Differentiators
- Three enable inputs for flexible cascading (vs 74HC138)
- Higher output sink current (8 mA) (vs 74HC138)
- Schottky-clamped TTL technology (vs 74HCT138)
Design Notes
Ensure the enable inputs are correctly biased: G1 must be high, and G2A and G2B must be low for the decoder to be active. If any enable is in the wrong state, all outputs will be high (inactive). Unused inputs should be tied to VCC or GND to prevent floating nodes, which can cause erratic behavior and increased power consumption.
Place decoupling capacitors (0.1 uF) close to the VCC and GND pins to reduce power supply noise. For high-speed applications, keep the traces from the select inputs and outputs short to minimize propagation delay and signal integrity issues. Use a solid ground plane to reduce noise coupling.
The SN74LS138 dissipates approximately 32 mW under typical conditions, which is negligible for thermal management. However, if driving multiple outputs at maximum sink current (8 mA each), the total power dissipation can increase. Ensure adequate airflow or copper area for heat dissipation if the device is used in a high-temperature environment.
Compliance Information
RoHS compliant per TI product page. Not AEC-Q100 qualified as it is a commercial logic device.
