TPS536C9T - Dual-Channel 12-Phase D-CAP+ Controller | TI
MPN: TPS536C9T ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.95 | $8.95 |
| 10 | $8.2 | $82.00 |
| 100 | $7.1 | $710.00 |
| 500 | $6.4 | $3,200.00 |
| 1,000 | $5.8 | $5,800.00 |
Drop-in alternatives for TPS536C9T — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
TPS536C9RSLR
✅ Drop-In✓ In Stock
$4.1 / Unit
View Datasheet →TPS536C9RSLR
✅ Drop-In✓ In Stock
$4.1 / Unit
View Datasheet →TPS536C9T Maximum Ratings & Electrical Characteristics
| Topology | Step-down multiphase buck controller (D-CAP+) |
| Channels | 2 (N + M <= 12 phases total) |
| Maximum Total Output Current | 765 A (with smart power stages) |
| Input Voltage Range | 4.5 V to 17 V |
| Output Voltage (minimum) | 0.25 V |
| Control Interface | PMBus, VR14 SVID |
| TLVR Support | Yes (trans-inductor voltage regulator) |
| Non-Volatile Memory | Built-in NVM configuration |
| Smart Power Stage Compatibility | TI smart power stages |
| Package | 48-VFQFN (RSL), 6.00 mm x 6.00 mm, exposed pad |
| Mounting Type | Surface Mount |
| Protection Features | OVP, OCP, OTP, fault management via PMBus |
| Telemetry | PMBus digital telemetry and monitoring |
| Applications Standard | Intel VR14 SVID compliant |
| RoHS Status | [DATA_NEEDED: RoHS status] |
| Operating Temperature | [DATA_NEEDED: operating temperature range] |
TPS536C9T Pin Configuration
| Pin 1 | VDD — Controller supply voltage [VERIFY: pin assignment per datasheet] |
| Pin 19 | SYNC/RESET — Synchronization / reset function; connection guidance per TI E2E thread 1566151 |
| Pin - | PWMx — Phase PWM outputs to smart power stages (up to 12 phases) |
| Pin - | CSxP/CSxN — Per-phase current sense inputs |
| Pin - | SCL/SDA — PMBus clock and data |
| Pin - | SVID_ALERT/SVID_CLK/SVID_DATA — VR14 SVID interface signals |
| Pin - | VSEN/FB — Output voltage feedback sense |
| Pin - | GND — Ground / exposed pad thermal connection |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this component. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
TPS536C9T is suitable for 6 applications: Server CPU Core Power (VR14), TLVR Evaluation and Transient Testing, ASIC and FPGA Accelerator Cards, Networking and Datacenter Equipment, High-Current Point-of-Load Conversion, Industrial Compute and Edge Servers.
Server CPU Core Power (VR14)
The TPS536C9T is VR14 SVID compliant, making it a natural fit for Intel server and workstation CPU core rails. Its 4.5 V to 17 V input accepts the 12 V platform rail directly, and the N + M <= 12 phase D-CAP+ architecture with TLVR support delivers the multi-hundred-amp (up to 765 A) step loads CPUs present. The SVID interface lets the CPU command voltage setpoints and operating modes in real time, while PMBus telemetry reports per-rail voltage, current, and temperature for platform health monitoring. Using TI smart power stages, designers achieve low-BOM-cost dense layouts in the 6 mm x 6 mm controller footprint.
Recommended
TLVR Evaluation and Transient Testing
For engineers characterizing 12-phase TLVR systems, the TPS536C9T pairs with electronic loads and load slammers to validate transient response, as discussed on TI's E2E forum for the TPS536C7EVM-051 platform. TLVR coupling enables extremely fast energy transfer during microsecond load steps, and the D-CAP+ controller modulates phase behavior to exploit this. The built-in NVM allows rapid reconfiguration of phase count and loop parameters without firmware host intervention. Designers should follow the datasheet layout guidance for SYNC/RESET and current-sense routing to get repeatable slammer test results.
Recommended
ASIC and FPGA Accelerator Cards
AI accelerators and high-end FPGA cards require core rails from 0.25 V upward at hundreds of amps. The TPS536C9T supports outputs down to 0.25 V and up to 765 A total across two channels, with dynamic current sharing that balances thermal stress across power stages. For cards without an SVID-capable host, the PMBus interface provides full runtime voltage scaling, margining, and fault handling. The D-CAP+ loop's fast transient response reduces required output capacitance, freeing board area in dense accelerator form factors such as OCP and PCIe cards.
Recommended
Networking and Datacenter Equipment
Switch, router, and storage systems use 12 V intermediate buses feeding multiple high-current point-of-load rails. The TPS536C9T's dual-channel architecture lets one controller serve two independent high-current rails (for example, ASIC core and SERDES/PHY rails), reducing controller count. PMBus telemetry integrates with shelf-management systems for predictive maintenance, and built-in NVM stores configuration without a host boot dependency. Its 4.5 V to 17 V input tolerance covers both 12 V and intermediate 5 V buses with margin, and protection features (OVP/OCP/OTP) support high-availability requirements.
Recommended
High-Current Point-of-Load Conversion
Any design converting a 4.5 V to 17 V bus to a sub-1 V, multi-hundred-amp rail benefits from the TPS536C9T's multiphase approach, which interleaves phases to cancel ripple and spread heat. Compared with paralleled single-phase converters, D-CAP+ provides inherent current sharing and faster transient response with less output capacitance. Designers pair the controller with TI smart power stages that integrate driver and FETs, shortening design time and improving efficiency at the low duty cycles typical of 12 V-to-0.8 V conversion. The 48-pin QFN keeps controller footprint minimal on crowded POL areas.
Recommended
Industrial Compute and Edge Servers
Rugged edge servers and industrial compute nodes running embedded CPUs still need VR14-class core power at reduced environmental budgets. The TPS536C9T's digital loop tolerates input variation across the 4.5 V to 17 V range from noisy industrial 12 V rails, and PMBus fault reporting supports remote diagnostics in unattended installations. NVM-stored configurations survive power cycles without host intervention, speeding brown-out recovery. Its SVID compliance covers embedded Intel processor families, and phase-count flexibility lets one controller design scale across product tiers from low to 12 phases.
Recommended
Recommended Products Summary
Engineering reference data for TPS536C9T — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | TPS536C9 | TPS536C9RSLR | TPS53622RSBT | ISL69269 |
|---|---|---|---|---|---|
| Package | 48-VFQFN (RSL) 6x6 mm | 48-VQFN (RSL) | 48-VQFN (RSL) | QFN (RSB) - different | [DATA_NEEDED] |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Renesas Electronics |
| Channels / Phases | 2 ch, N+M <= 12 | 2 ch, N+M <= 12 | [DATA_NEEDED] | 2 ch | [DATA_NEEDED] |
| Input Voltage | 4.5 V to 17 V | 4.5 V to 17 V | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| TLVR Support | Yes | No | [DATA_NEEDED] | No | [DATA_NEEDED] |
| VR14 SVID Interface | Yes | Yes | [DATA_NEEDED] | No | SVID-capable (verify variant) |
| Built-in NVM | Yes | Yes | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Max Output Current (with stages) | 765 A | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Lifecycle Status | Active | Active | Active | Active | Active |
Key Differentiators
- TLVR topology support (vs TPS536C9)
- VR14 SVID compliance with PMBus (vs TPS53622RSBT)
- Built-in NVM configuration (vs ISL69269)
Design Notes
Place the TPS536C9T close to the smart power stages and route each PWM output short and direct to minimize ringing. Per TI's datasheet layout section and E2E guidance, Kelvin-connect per-phase current sense (CSxP/CSxN) directly at the power stage sense points and keep the SYNC/RESET pin (pin 19) termination per datasheet recommendations. Use solid ground planes under the controller with the exposed pad soldered to a via-stitched thermal pad.
For TLVR designs, the auxiliary (ac-coupled) TLVR inductors and phase arrangement N+M strongly influence transient performance. D-CAP+ allows reduced output capacitance, but validate worst-case load steps (e.g., with an electronic load or load slammer) at maximum and minimum output voltage setpoints commanded over SVID. Confirm the smart power stage current ratings aggregate to your peak load with margin below the 765 A class ceiling.
NVM default configuration must match your phase assignment before first power-up - a mismatched phase map can trigger fault shutdowns. Also ensure SVID boot sequencing meets the platform's VR14 requirements: the CPU expects specific voltage presence before SVID handshake. If PMBus and SVID are both used, resolve interface arbitration in system firmware to avoid conflicting voltage commands.
Compliance Information
Compliance details not present in provided web data; verify on TI product page quality section.
