EP20K400CF672C-7ES vs EP20K400CF672C-8 Comparison
Detailed side-by-side comparison of EP20K400CF672C-7ES by Altera and EP20K400CF672C-8 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K400CF672C-7ES - 400K Gates APEX 20KC FPGA | Altera | 672-BGA
EP20K400CF672C-7ES ObsoleteSpecification Comparison
| Parameter | EP20K400CF672C-7ES | EP20K400CF672C-8 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $132.00 | $95.00 |
| Family | APEX 20KC | APEX 20K |
| Series | EP20K400 | β |
| System Gates | 400,000 | β |
| Logic Elements | 16,640 | 16,640 |
| Embedded Memory (bits) | 212,992 | β |
| Maximum User I/O | 488 | 488 |
| Number of PLLs | 4 | β |
| Embedded Array Blocks (EABs) | [DATA_NEEDED: EAB count from datasheet] | β |
| Process Technology | 0.15 um CMOS | 0.15 Β΅m all-layer copper CMOS |
| Core Voltage | 1.8 V | β |
| Speed Grade | -7 | -8 |
| Maximum Internal Clock Frequency | 375.94 MHz | β |
| Propagation Delay (per Sierra IC) | 1.400 ns | β |
| Operating Temperature Range | 0 C to 85 C (commercial) | β |
| Package | 672-BGA (FineLine BGA, 1.00 mm pitch) | β |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Configuration Support | EPC16, EPC8, EPC4, EPC2, EPC1 serial devices; JTAG | β |
| Typical Gates | β | 400,000 |
| Macros | β | 1,664 |
| Number of I/O Banks | β | [DATA_NEEDED: number of I/O banks] |
| Package Type | β | PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) |
| Core Voltage (VCCINT) | β | 1.8 V nominal (1.71 V to 1.89 V) |
| I/O Voltage (VCCIO) | β | [DATA_NEEDED: VCCIO options] |
| Pin-to-Pin Delay (tPD) | β | 1.78 ns (speed grade -8) |
| Temperature Grade (C) | β | Commercial, 0 Β°C to 85 Β°C |
| Embedded Memory Type | β | ESB (RAM / ROM / CAM) |
| Configuration Interface | β | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel |
| JTAG Support | β | Yes (IEEE 1149.1 boundary-scan) |
| MSL Level | β | [DATA_NEEDED: MSL level] |