EP20K400CF672C-8 vs EP20K400CF672C7ES Comparison

Detailed side-by-side comparison of EP20K400CF672C-8 by Altera and EP20K400CF672C7ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K400CF672C-8 EP20K400CF672C7ES
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $95.00 $152.00
Family APEX 20K APEX 20KC
Logic Elements 16,640 β€”
Typical Gates 400,000 β€”
Macros 1,664 β€”
Maximum User I/O 488 488
Number of I/O Banks [DATA_NEEDED: number of I/O banks] β€”
Package Type PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) 672-ball FineLine BGA
Core Voltage (VCCINT) 1.8 V nominal (1.71 V to 1.89 V) β€”
I/O Voltage (VCCIO) [DATA_NEEDED: VCCIO options] β€”
Pin-to-Pin Delay (tPD) 1.78 ns (speed grade -8) β€”
Speed Grade -8 C7 (commercial, -7)
Temperature Grade (C) Commercial, 0 Β°C to 85 Β°C β€”
Process Technology 0.15 Β΅m all-layer copper CMOS 0.18 um CMOS
Embedded Memory Type ESB (RAM / ROM / CAM) β€”
Configuration Interface JTAG (IEEE 1149.1), Passive Serial, Passive Parallel β€”
JTAG Support Yes (IEEE 1149.1 boundary-scan) β€”
Mounting Type Surface Mount (BGA) Surface Mount
RoHS Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance]
MSL Level [DATA_NEEDED: MSL level] β€”
Series β€” EP20K400
Device Type β€” Loadable PLD / FPGA
Logic Elements (Cells) β€” 16,640
System Gates β€” 400,000
Embedded Memory (Bits) β€” 212,992
Total RAM Bits β€” 212,992
I/O Lines β€” 484
Input Lines β€” 488
Number of PLLs β€” 4
Maximum Internal Clock Frequency β€” 375.94 MHz
Propagation Delay β€” 1.4 ns
Core Voltage β€” 1.8 V
MultiVolt I/O β€” 1.5 V / 1.8 V / 2.5 V / 3.3 V
Operating Temperature β€” 0C to +85C (commercial)
Package Code β€” FC-FBGA-B672
Ball Pitch β€” 1.000 mm

Datasheets & Resources

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